Next Article in Journal
Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error
Next Article in Special Issue
Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory
Previous Article in Journal / Special Issue
Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime
J. Low Power Electron. Appl. 2014, 4(1), 26-43; doi:10.3390/jlpea4010026

Design of Processors with Reconfigurable Microarchitecture

* ,
School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU, UK
* Author to whom correspondence should be addressed.
Received: 2 October 2013 / Revised: 6 January 2014 / Accepted: 8 January 2014 / Published: 20 January 2014
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
View Full-Text   |   Download PDF [681 KB, uploaded 20 January 2014]   |   Browse Figures


Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.
Keywords: microarchitecture; microprocessor; reconfigurability; power proportionality; Conditional Partial Order Graphs microarchitecture; microprocessor; reconfigurability; power proportionality; Conditional Partial Order Graphs
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

Share & Cite This Article

Further Mendeley | CiteULike
Export to BibTeX |
EndNote |
MDPI and ACS Style

Mokhov, A.; Rykunov, M.; Sokolov, D.; Yakovlev, A. Design of Processors with Reconfigurable Microarchitecture. J. Low Power Electron. Appl. 2014, 4, 26-43.

View more citation formats

Article Metrics

For more information on the journal, click here


[Return to top]
J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert