Special Issue "Selected Papers from FTFC 2013 Conference"

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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (30 September 2013)

Special Issue Editors

Guest Editor
Prof. Dr. Amara Amara

Institut Supérieur d'Electronique de Paris (ISEP), France
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Guest Editor
Prof. Dr. Alex Yakovlev

School of Electrical, Electronic and Computer Engineering, Newcastle University, UK
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Guest Editor
Dr. Olivier Thomas

Laboratoire d'électronique des technologies de l'information (CEA-Leti), France
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Guest Editor
Dr. Costin Anghel

Institut Supérieur d'Electronique de Paris (ISEP), France
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Special Issue Information

Dear Colleagues,

This special issue covers the advances in designing low-voltage low-power systems from manufacturing process and circuit simulation to tools and synthesis or system-level design and optimization. The fields of application are numerous, including distributed networks, sensors, implants, SOCs, and embedded systems.

Topics of interest for this issue include, but are not limited to:

  • technologies and emerging technologies for low power and low voltage, variability issues
  • wireless communication circuits and networks, RF circuits
  • digital, analog and mixed-signal circuits
  • power management and power optimization techniques
  • ultra low power implants, sensors, body area networks and wearable computing
  • low voltage and low power computer-aided design

Prof. Dr. Amara Amara, Prof. Dr. Alex Yakovlev, Dr. Olivier Thomas and Dr. Costin Anghel
Guest Editors

Submission

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. Papers will be published continuously (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are refereed through a peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed Open Access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 300 CHF (Swiss Francs). English correction and/or formatting fees of 250 CHF (Swiss Francs) will be charged in certain cases for those articles accepted for publication that require extensive additional formatting and/or English corrections.


Published Papers (5 papers)

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Research

Open AccessArticle Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory
J. Low Power Electron. Appl. 2014, 4(3), 214-230; doi:10.3390/jlpea4030214
Received: 18 October 2013 / Revised: 9 March 2014 / Accepted: 20 March 2014 / Published: 28 August 2014
Cited by 1 | PDF Full-text (2961 KB) | HTML Full-text | XML Full-text
Abstract
Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage
[...] Read more.
Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC. Full article
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
Open AccessArticle Design of Processors with Reconfigurable Microarchitecture
J. Low Power Electron. Appl. 2014, 4(1), 26-43; doi:10.3390/jlpea4010026
Received: 2 October 2013 / Revised: 6 January 2014 / Accepted: 8 January 2014 / Published: 20 January 2014
Cited by 4 | PDF Full-text (681 KB) | HTML Full-text | XML Full-text
Abstract
Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation
[...] Read more.
Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor. Full article
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
Open AccessArticle Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime
J. Low Power Electron. Appl. 2014, 4(1), 15-25; doi:10.3390/jlpea4010015
Received: 30 September 2013 / Revised: 18 December 2013 / Accepted: 3 January 2014 / Published: 10 January 2014
PDF Full-text (598 KB) | HTML Full-text | XML Full-text
Abstract
This paper describes the performance prospect of scaled cross-current tetrode (XCT) CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher) stems from
[...] Read more.
This paper describes the performance prospect of scaled cross-current tetrode (XCT) CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher) stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery. Full article
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
Open AccessArticle Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM)
J. Low Power Electron. Appl. 2014, 4(1), 1-14; doi:10.3390/jlpea4010001
Received: 25 October 2013 / Revised: 6 December 2013 / Accepted: 9 December 2013 / Published: 9 January 2014
Cited by 4 | PDF Full-text (782 KB) | HTML Full-text | XML Full-text
Abstract
Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully
[...] Read more.
Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. Full article
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
Open AccessArticle Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits
J. Low Power Electron. Appl. 2013, 3(4), 368-384; doi:10.3390/jlpea3040368
Received: 30 September 2013 / Revised: 29 November 2013 / Accepted: 6 December 2013 / Published: 16 December 2013
Cited by 3 | PDF Full-text (412 KB) | HTML Full-text | XML Full-text
Abstract
This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such circuits.
[...] Read more.
This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1-dimensional reduced order model (ROM) of the switch; the results given by this simplified model are compared to classical CMOS-based, and sub-threshold CMOS-based adiabatic logic circuits. NEMS-based circuits and CMOS-based circuits show different optimum operating conditions, depending on the device parameters and circuit operating frequency. Full article
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)

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