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J. Low Power Electron. Appl. 2014, 4(1), 15-25; doi:10.3390/jlpea4010015

Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

1
Organization for Research and Development of Innovative Science and Technology (ORDIST), Kansai University, Yamate-cho, Suita 564-8680, Japan
2
Graduate School of Science and Engineering, Kansai University, Yamate-cho, Suita 564-8680, Japan
*
Author to whom correspondence should be addressed.
Received: 30 September 2013 / Revised: 18 December 2013 / Accepted: 3 January 2014 / Published: 10 January 2014
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
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Abstract

This paper describes the performance prospect of scaled cross-current tetrode (XCT) CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher) stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery. View Full-Text
Keywords: XCT-SOI MOSFET; quasi-static body floating effect; source potential floating effect; low energy; medical applications XCT-SOI MOSFET; quasi-static body floating effect; source potential floating effect; low energy; medical applications
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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MDPI and ACS Style

Omura, Y.; Sato, D. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime. J. Low Power Electron. Appl. 2014, 4, 15-25.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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