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Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime
J. Low Power Electron. Appl. 2014, 4(1), 26-43; doi:10.3390/jlpea4010026

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Article Published20 January 2014 09:43 CET
article pdf uploaded.20 January 2014 09:44 CET
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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert