Figure 1 shows the block diagram of the IC which acts as recording and transmitting module. The circuit consists of 16 low-noise amplifiers (LNAs), which perform low-power and low-noise amplification of neural signals. The amplifier outputs are sampled by a time-division multiplexer (TDM) at 20 kS/s onto one data lead before being further amplified by a variable-gain amplifier (VGA) and converted by an 8 bit successive approximation register (SAR) analog to digital converter (ADC). The digital data are then processed by a logic block, performing data compression, assembly and Manchester encoding of the bit stream. Finally, the digital signal is sent to a 400 MHz binary FSK wireless transmitter based on direct modulation of a Voltage Controlled Oscillator (VCO), enabling a 1.25 Mbit/s data rate. A crystal Clapp oscillator employing an external 20 MHz quartz and a power-on/reset (POR) circuit complete the system, providing a clean 20 MHz frequency clock and a synchronization signal at the start-up. It is worth pointing out that, to reduce silicon area and costs, only 16 amplifiers have been integrated. The remaining 48 channels have been added by connecting a voltage reference to the multiplexer input. In this way all the stages following the amplifier array are designed to process signals from a 64 channel front-end, thus making it possible to reliably assess the actual performance of a complete 64 channel system.

The receiver (see Figure 2) consists of a quadrature zero-IF down-converter (MAX3580) using an LNA with a noise figure of 4.7 dB at 400 MHz, RF and baseband tunable filters and automatic gain control circuits. The quadrature signals are converted by a dual channel, 20 MSps, 10 bit ADC (AD9201) and fed to a Xilinx FPGA module (OpalKelly, XEM3005), which performs frequency demodulation and Manchester decoding and sends the received data to a PC via a USB link. In addition, a Graphical User Interface (GUI) based on Labview/C software was implemented to allow data saving and on-line elaboration.

Amplification and filtering of the input signal are performed by a three-stage circuit shown in Figure 3. The first stage is an AC-coupled high-pass filter, using two MOS-bipolar pseudo-resistors as feedback elements [10], which enables the synthesis of high-value resistances without using large-area components. The mid-band amplifier gain is given by , set to –67 by taking pF and C₂ = 150 fF. The high-pass pole frequency is placed below 10 Hz to reject the offset and the slow voltage drift of the electrode. A tunable G_M -C high-pass filter with a cut-off frequency f_HP of about 300 Hz is introduced after the first stage. It is designed to reject the low-frequency signals, such as Local Field Potentials (LFPs) in the Hz frequency range that can prevent a correct detection of the neural spikes or even saturate the amplifier, and cuts off the input-referred noise due to the pseudo-resistors of the first amplification stage. After the selective high-pass filter, a second non-inverting gain stage is added to provide further signal amplification and to define the high frequency cut-off, f_LP. The stage is a single-ended capacitive-coupled voltage amplifier with a gain , achieved by using pF and fF. A capacitive-coupled structure was preferred to a purely resistive feedback amplifier to minimize the current drawn by the OTA output stage. The DC voltage at the amplifier input is determined by the pseudo-resistor elements in the feedback path, while the low-pass cut-off frequency is set by the gain-bandwidth product of the operational amplifier (GBWP₂ ) to about kHz. Note that at very low frequencies this non-inverting stage has a unity gain in order not to amplify the offset of the operational amplifier.

The multiplexed and amplified signal is then converted into a digital form by an 8 bit SAR ADC (see Figure 1). This topology is well-suited for low power and small-area applications since it requires a minimal amount of analog circuitry. To save area, analog multiplexing of input signals, requiring only one AD converter, was employed even though it resulted in a small power penalty with respect to the use of one converter per each amplifier and digital multiplexing of data [16].

The number of the converter bits was chosen taking into account the following considerations:

The maximum amplitude for an extra cellular action potential is ~ 1 mV [17] while the minimum signal is about 10 μV, the latter being determined by the typical input noise due to neural background activity and electrode impedance [18]. Therefore, the ratio between the Full Scale Range (FSR) and the ADC least significant bit, i.e., the dynamic range of the converter, should be better than 1 mV/10 μV 100 . This results in a converter resolution larger than 6.35 bit.

In practice, taking into account that the effective number of bit (ENOB) is always lower than the nominal figure, the use of an 8 bit ADC will provide a safe margin for the design. A higher resolution is useless and harmful since it would increase the ADC power consumption.

The ADC consists of three main parts: the capacitor array, the comparator and the logic block performing the successive-approximation algorithm. The capacitor array, which acts as sampling capacitance during the sampling interval and as charge-sharing DAC during the conversion period, has been implemented as a binary array. The value of the unit capacitance, C_LSB, was chosen considering two requirements:

The noise in the sampling phase has to be significantly smaller than the quantization noise. Thus, the total capacitance of the array, C_TOT, must satisfy the condition: (19) which clearly is not a limit factor, resulting in C_TOT much larger than about 1 fF.

The implemented data reduction system takes advantage of the low duty cycle of the neural activity to eliminate transmission of useless signal containing only noise. Spike duration and firing rates are typically lower than 1 ms and 100 Hz [22], respectively. A finite-state machine (FSM in Figure 6) compares each incoming digital sample with a user-programmable digital threshold, i.e., an 8 bit word stored in the embedded SRAM. When the threshold is crossed, 20 samples of the signal from the same channel are recorded, covering a 1 ms time frame (see Figure 7). This strategy was chosen taking into account that a clear identification of APs requires the detection of three features, namely the amplitude of the peak and the trough and the time interval between them [22], which can be extracted with enough resolution by using 20 samples, even for the fastest spikes. The threshold can be set by the user before the recording starts, choosing among four predefined digital words: “x1000000 ”, “x0100000 ”, “x0010000 ” and “x0001000 ” (corresponding to 1/2, 1/4, 1/8 and 1/16 of half the ADC full scale range). Since the spike can have a first peak either positive or negative and the baseline is at the middle of the ADC range, the threshold is either positive and negative for each sample. For example, considering the first threshold, the FSM is triggered if the incoming sample is larger than “11000000 ” or lower than “01000000 ”. If the gain of the amplification chain is set to the maximum value (83 dB 14000 ), these four thresholds correspond to an input-referred amplitude of ± 54 μV, ± 27 μV, ± 13 μV and ± 7 μV.

The recorded samples are stored in a 2 kbit embedded memory (SRAM in Figure 6) together with the channel address and the timing stamp, both with a 8 bit resolution. Each spike is then compressed in 22 bytes. The SRAM is continuously read at 1 Mbit/s rate by the control logic block, which adds service bits for synchronization at the receiver and then performs Manchester encoding of the bit stream. The final data rate reaching the transmitter is 1.25 Mbit/s. The memory read speed was determined by taking into account two aspects:

the lower the read speed, the higher the compression factor is; 1 Mbit/s read speed results in a compression factor of 10 (from 10.24 Mbit/s, corresponding to 64 channels sampled at 20 kHz per channel and 8 bit per sample, to 1.25 Mbit/s data rate) and allows saving a considerable amount of power and bandwidth at the transmitter side;

The memory was sized to reduce missed spikes when burst activity is present. Monte-Carlo simulations were performed considering that the neural firing rate follows a Poisson statistics. Figure 8 shows the missing spike percentage as a function of the average firing rate for each of the 64 channels and for different memory sizes. Opting for 1 Mbit/s read speed and 2 kbit RAM size, the missing spike percentage is less than 0.1% for 64 channels firing at 50 spikes/s and less than 10% for all channels firing at 100 spikes/s. With these choices, the memory is able to store spikes that occur in the same 1 ms frame in 11 consecutive channels before missing a spike. Each AP is transmitted, once completely stored, in 176 μs and thus the worst-case latency time (time difference between the detection and the transmission of an AP) is about 2.9 ms, which is not an issue both in neuroscience experiments and in future prosthetic applications [23].

The validity of the data-reduction algorithm was tested by running a custom clustering software that employed fuzzy c-means spike sorter [24,25] on a data set from a public source [26] with spike waveforms hardly distinguishable one from each other (see Figure 9). The ratio between the peak-to-peak spike amplitude and the rms noise was approximately 10 . Clustering based on Principal Component Analysis (PCA) was performed on original data containing spikes from three different neurons and on the same data but reduced according to the above windowing strategy. Figure 9 shows that clustering on the reduced data set leads to clear separation of the three spike families, with identification errors reported in Table 2. Two types of error occur in a PCA-based clustering: type I errors occur when APs from two different neurons are grouped together (false positives), whilst type II errors occur when not all APs generated by one neuron are grouped together (false negatives). When applied to the original dataset, the PCA-based identification procedure leads to type I/type II mean error rates of 4.1%–5.2%, respectively. The reduced data sets showed 4.6%–5.3% values, thus demonstrating that the reduction strategy preserves the quality needed for effective neuron identification. These results are not surprising considering that, as stated in [22], more than 80% of neural spike information is carried by three analog features of the AP waveform, namely the peak and the through amplitudes and the time between them. The results of spike sorting using these analog features [27] and performed on the same trace are also reported in Table 2. Note that the compression method employed in this work always outperforms the clustering obtained using only these three features. Finally, it is worth nothing that the current consumption of the overall digital signal processing is limited to about 400 μA, most of which consumed by the finite-state machine.

The 1.25 Mbit/s bit stream is transmitted using a Manchester-coded binary Frequency Shift Keying (MC-2FSK) modulation at a carrier frequency of 400 MHz. The transmitter (see Figure 10) consists of a voltage-controlled oscillator (VCO) directly modulated by the digital data, inserted in a Phased-Locked Loop (PLL). Since the modulator is a power-hungry system, the design of the whole PLL, and in particular of the high-frequency oscillator, has to be carried out with great care.

The oscillator has a current-biased topology with double cross-coupled pair transconductor. This oscillator architecture allows to minimize the current consumption for a given phase noise with respect to the topology featuring a single differential pair transconductor [28]. In order to accurately set the PLL output frequency at the desired value of 400 MHz and to compensate for process, temperature and power-supply variations, the oscillator has to span over ±10% of its central frequency, i.e., a band of about ±40 MHz. This means that the capacitance has to be varied as: (21) f₀ is the central oscillation frequency (400 MHz), the covered band of 80 MHz and C the tank capacitor. To make the oscillation frequency insensitive to the parasitic capacitance of the active devices, routing, pads and package pins (the inductor is off-chip), the tank capacitance has to be set in the pF range. Thus, we designed the oscillator with C tunable from 6 pF to 11 pF, determining an inductance value of about 20 nH. The tank capacitance is implemented by three digitally-controlled binary-weighted NMOS inversion-mode varactors that perform coarse tuning of the oscillation frequency and an analog NMOS inversion-mode varactor for fine-tuning of the frequency, enabling to close the loop of the PLL. Another small NMOS varactor is also adopted for frequency modulation.

Once the tank parameters have been determined, the current I_BIAS of the tail generator and the (W/L) ratio of the pair transistors have to be chosen taking into account the following considerations:

The small-signal loop gain or excess gain [29] of the oscillator (g_mR_TANK, where g_m is the small-signal transconductance of the double differential-pair and R_TANK is the tank equivalent parallel resistance) has to be larger than 1 in order to assure the oscillation start-up. Since the common-mode output voltage of the oscillator is set to the half of the power supply to maximize the oscillation swing, i.e., V, we have: (22) corresponding to a current larger than μA. Note that in Equation (22) it was assumed that the overall transconductance g_m of the double differential-pair is equal to the single MOS transconductance and that NMOS and PMOS transistors have the same overdrive voltage, V_ov = = V 0.8 V.

For μA, C in the 6–11 pF range and , the excess gain is approximately 2 and the oscillation amplitude is larger than 2 V, preventing the tail current generator to enter the ohmic region and avoiding a phase noise degradation. Moreover, these choices ensure that the phase noise is not an issue being better than 1–50 dBc/Hz at 1 MHz frequency offset.

The VCO is followed by a cascade of a divide-by-2 dynamic logic prescaler and a static modulo-10 CMOS counter, which further divides the frequency by 10 . The PLL reference is the same 20 MHz master clock, allowing the loop to set the oscillation frequency at 20 times the reference clock, i.e., 400 MHz. The PLL also includes a phase-frequency detector with a charge-pump driving an RC -C off-chip filter (see Figure 10), which sets the loop bandwidth to 50 kHz. Excluding the VCO, the power consumption is mainly due to the high-frequency prescaler, which draws more than 200 μA. The current consumption of the whole synthesizer is about 700 μA.

The synthesizer frequency is modulated in an open-loop mode by the data at 1.25 MHz, i.e., at 1.25 Mbit/s rate with Manchester encoding. Thus, the loop is open for the frequency modulation since the PLL bandwidth is significantly lower than the bit-rate. This prevents the PLL to filter out the induced frequency modulation. The only purpose of the loop is to fix the central oscillation frequency in order to avoid frequency drift due to temperature and power supply variations. To limit the occupied bandwidth, a frequency deviation of about ±400 kHz was adopted. Considering a modulation frequency of 1.25 MHz, this value corresponds to a modulation index of 0.64. The bandwidth of the transmitted signal is determined by the Carson rule [32]: (25) where and f_m are the peak frequency deviation (400 kHz) and the frequency modulation (1.25 MHz), respectively.

The transmitter is completed by a class-AB power amplifier (PA) that drives a 50- antenna via an off-chip resonant filter. The PA consists of an open-drain PMOS transistor directly connected to the oscillator output, sized in order to draw about 3.5 mA. Thus, the power delivered to the antenna is about 0 dBm considering a reasonable efficiency of 10%. The output power, and thus the power consumption of the PA, were set after estimating the sensitivity of the receiver, which depends on the modulation type, the signal bandwidth and the noise factor of the receiver itself. The receiver input noise in the signal bandwidth of 3 MHz is: (26) where F is the noise factor of the receiver, which was assumed to be equal to 10 dB in the above equation. For a low modulation index Manchester-encoded modulation, the SNR required at the receiver input to ensure a bit error rate (BER ) lower than is dB [33]. Thus the input power needed at the receiver is: (27) Once the receiver sensitivity has been computed, it is possible to set the PA power to achieve a desired transmission range. Taking into account the Friis transmission equation, the ratio of power available at the input of the receiving antenna, P_R, to the output power of the transmitting antenna, P_T, is: (28) where G_T and G_R are the gains with respect to an isotropic radiator of the transmitting and receiving antennas, respectively, is the wavelength, and d is the distance between the antennas. While the receiver antenna is a dipole antenna and its gain can be estimated to be 0 dB, the transmitter antenna is a whip antenna with a gain that can be as low as –20 dB. Note that Equation (28) represents the power at the receiver antenna that is supposed to be matched with the receiver. Thus, the receiver input power is 3 dB lower. Thus, considering Equation (28) and setting the maximum transmission distance to 10 m, the power needed at the transmitter antenna is 11 dBm, where a 3 dB factor accounting for the matching between the receiver antenna and the receiver itself is considered. Finally, to have a safety margin, a PA featuring a 0 dBm output power was designed.

The chip was fabricated in AMS 0.35 μm, 3 V 4M2P CMOS process and occupies a total area of mm², pads included (see Figure 11). The preamplifier has a mid-band gain of about 65 dB, a high frequency cut-off of 10.5 kHz and a low-frequency cut-off tunable from 1 Hz to 1 kHz (see Figure 12). The input-referred noise, for Hz, is 3.05 μV, while the current consumption is 4 μA for the first stage, 0.001 μA and 0.3 μA for the high-pass filter and the second amplifying stage respectively, resulting in an overall NEF of 2.5. The input-referred power spectral density is shown in Figure 13 for different values of the G_M -C filter high-pass corner frequency. The plateau of –152 dBV² /Hz corresponds to an input-referred noise of about (25 nV)² /Hz, close to the expected value. Note that, for Hz, the input-referred noise is mainly due to the G_M -C high-pass filter, as predicted by Equation (14). The common-mode rejection ratio (CMRR ) and the power supply rejection ratio (PSRR ) of the overall pre-amplifier are higher than 65 dB and 50 dB, respectively, while the cross-talk between adjacent channels due to the analog multiplexing is lower than –40 dB.

With regard to the AD converter, Figure 14 shows the results of static measurements. The converter features a DNL less than 0.45 LSB and an INL less than 1 LSB. Figure 15 shows the output spectrum of the ADC for a full-scale sine wave at 1 kHz frequency as input signal. The signal to noise plus distortion ratio (SNDR) is close to 45 dB, and the number of effective bit (ENOB) is thus about 7.2.

Considering the modulator, the frequency range covered by the VCO spans from 310 to 460 MHz (see Figure 16), allowing to lock the PLL loop to a frequency of 400 MHz frequency even with a large spread of tank component values and for sizable variations in power supply and temperature. When no data modulation is performed, the modulator phase noise (see Figure 17) is less than –123 dBc/Hz at 1 MHz offset from the carrier. The phase noise spectrum has a typical low-pass shape, with 50 kHz cut-off frequency, since it is completely dominated by the charge-pump noise [34], while the VCO phase noise is much lower. The rms integral frequency noise of the modulator in the 10 Hz to 10 kHz band is less than 3 kHz (see the residual frequency FM in Figure 17), whereas the output spectrum of the synthesizer when acting as frequency modulator is depicted in Figure 18: more than 98% of the signal power is included in a 3 MHz band.

For a whip antenna at the transmitter and a dipole antenna at the receiver side, the received power in a free space is shown in Figure 19. The sensitivity of the receiver has been measured to be –74 dBm for a BER of , close to the estimated theoretical value predicted by Equation (27) of –79 dBm, allowing a transmission range larger than 30 m. The system has also been successfully tested for a 10 m distance between transmitter and receiver in a hostile environment as a neuroscience laboratory, giving a PA efficiency of about 7% while delivering a –2 dBm at a 50- output load. Disabling the PA, the tank inductor may act as transmitting antenna; in such measurements about –70 dBm was received by a loop antenna placed at approximately 5 cm from the tank inductor.

The overall performance of the implemented system is provided in Table 3. The power consumption of the presented circuit has been computed by projecting the performance to a complete 64 channel system. To this end, the additional budget needed for the missing 48 amplifiers has been added to the actual power consumption (16.6 mW) leading to 17.2 mW (6.7 mW with the PA turned off). The estimate is fair since all the other circuit blocks work with the same data rate of a full 64 channel system.

Figure 20 shows the system mounted on a rat for in vivo signal acquisition. It consists of two parts, a wireless neural recording headstage and a backpack. To limit disturbances collected from the environment, a small board ( cm² and 4.5 g of weight) is directly connected to a 16 channel microelectrode array (Tucker-Davis), with an impedance in the 20–60 k range at 1 kHz, implanted into the somatosensory cortex of an adult rat. The board includes the packaged chip and 10 external small surface-mount components (0805 or 0603 footprint): the VCO inductor, the power-amplifier resonant filter components (2 capacitors and 1 inductor), the 20 MHz quartz, the PLL loop-filter (1 resistor and 2 capacitors) and 2 decoupling capacitors between power supplies. The antenna is a quarter-wavelength whip antenna: it consists of a piece of wire about 17 cm long, easily placed along the back of the rat. The backpack has a weight of 40 g and includes two AAA batteries with 1000 mA/h capacity that may allow neural activity recordings for more than 100 hours. The two batteries are connected via three 10 cm long wires to the headstage. At the beginning of the in vivo experiment, the quality of the signals from the implanted electrodes was analyzed using a commercial acquisition system by recording the raw signals and noise from the same 16 electrode channels. The recorded traces featured a noise of about 10 μV_rms on all channels. The threshold of the digital peak processor was set to “x1000000 ” and the gain of the overall amplifying chain to the maximum value (83 dB) since the peak-to-peak spike amplitude was always lower than 100 μV. Thus, the digital threshold corresponds to an input-referred amplitude of about ±30 μV, i.e., ±3 times the rms noise. The high-pass cut-off frequency of the front-end amplifiers was set to about 300 Hz to properly reject the low-frequency signals and the power-line noise, enabling correct spike detection. The receiver dipole antenna has been placed at two meters from the rat while neural activity was recorded. Figure 21 shows a single trace recorded during the experiment and two spike waveforms extracted from the data stream, while in Figure 22 a large number of spikes recorded on the same channel are shown aligned in time.