Table of Contents

Abstract: We have found the following error in the title of this article which was recently published in J. Low Power Electron. Appl. [...]

Abstract: This paper reports a multi-channel neural spike recording system-on-chip with digital data compression and wireless telemetry. The circuit consists of 16 amplifiers, an analog time-division multiplexer, a single 8 bit analog-to-digital converter, a digital signal compression unit and a wireless transmitter. Although only 16 amplifiers are integrated in our current die version, the whole system is designed to work with 64, demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. Compression of the raw data is achieved by detecting the action potentials (APs) and storing 20 samples for each spike waveform. This compression method retains sufficiently high data quality to allow for single neuron identification (spike sorting). The 400 MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way, a 1:25 Mbit/s data rate is delivered within a limited band of about 3 MHz. The chip is realized in a 0:35 µm AMS CMOS process featuring a 3 V power supply with an area of 3:1 x 2:7 mm2. The achieved transmission range is over 10 m with an overall power consumption for 64 channels of 17:2 mW. This figure translates into a power budget of 269 µW per channel, in line with published results but allowing a larger transmission distance and more efficient bandwidth occupation of the wireless link. The integrated circuit was mounted on a small and light board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries, the system can continuously work for more than 100 hours allowing for long-lasting neural spike recordings.

Abstract: A low power adaptive digital baseband architecture is presented for a low-IF receiver of IEEE 802.15.4-2006. The digital section’s sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle the worst case conditions. We show that in a 0.13 μm CMOS technology, for an adaptive digital baseband section of the receiver, power saving can be up to 85% (0.49mW against 3.3mW) in favorable interference and signal conditions. The proposed concepts in the design are tested using a receiver test setup where the design is hosted on a FPGA.

Abstract: This paper reviews the direct connection of sensors to microcontrollers without using any analogue circuit (such as an amplifier or analogue-to-digital converter) in the signal path, thus resulting in a low-cost, lower-power sensor electronic interface. It first discusses the operating principle and explains how resistive and capacitive sensors with different topologies (i.e., single, differential and bridge type) can be directly connected to a microcontroller to build the so-called direct interface circuit. It then shows some applications of the proposed circuits using commercial devices and discusses their performance. Finally, it deals with the power consumption and proposes some design guidelines to reduce the current consumption of such circuits in active mode.

Abstract: This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire.