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Power Scalable Radio Receiver Design Based on Signal and Interference Condition
Signal Processing Lab, KTH Royal Institute of Technology, SE-100 44 Stockholm, Sweden
ECE Department, Indian Institute of Science, Bangalore 560 012, India
* Author to whom correspondence should be addressed.
Received: 10 August 2012; in revised form: 4 October 2012 / Accepted: 15 October 2012 / Published: 23 October 2012
Abstract: A low power adaptive digital baseband architecture is presented for a low-IF receiver of IEEE 802.15.4-2006. The digital section’s sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle the worst case conditions. We show that in a 0.13 μm CMOS technology, for an adaptive digital baseband section of the receiver, power saving can be up to 85% (0.49mW against 3.3mW) in favorable interference and signal conditions. The proposed concepts in the design are tested using a receiver test setup where the design is hosted on a FPGA.
Keywords: adaptive receiver; low power; receiver algorithms; packet based communication; sampling clock; word-length
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Dwivedi, S.; Amrutur, B.; Bhat, N. Power Scalable Radio Receiver Design Based on Signal and Interference Condition. J. Low Power Electron. Appl. 2012, 2, 242-264.
Dwivedi S, Amrutur B, Bhat N. Power Scalable Radio Receiver Design Based on Signal and Interference Condition. Journal of Low Power Electronics and Applications. 2012; 2(4):242-264.
Dwivedi, Satyam; Amrutur, Bharadwaj; Bhat, Navakanta. 2012. "Power Scalable Radio Receiver Design Based on Signal and Interference Condition." J. Low Power Electron. Appl. 2, no. 4: 242-264.