- freely available
JLPEA 2012, 2(4), 211-241; doi:10.3390/jlpea2040211
Abstract: This paper reports a multi-channel neural spike recording system-on-chip with digital data compression and wireless telemetry. The circuit consists of 16 ampliﬁers, an analog time-division multiplexer, a single 8 bit analog-to-digital converter, a digital signal compression unit and a wireless transmitter. Although only 16 ampliﬁers are integrated in our current die version, the whole system is designed to work with 64, demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. Compression of the raw data is achieved by detecting the action potentials (APs) and storing 20 samples for each spike waveform. This compression method retains sufﬁciently high data quality to allow for single neuron identiﬁcation (spike sorting). The 400 MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way, a 1.25 Mbit/s data rate is delivered within a limited band of about 3 MHz. The chip is realized in a 0.35 µm AMS CMOS process featuring a 3 V power supply with an area of 3.1 × 2.7 mm2 . The achieved transmission range is over 10 m with an overall power consumption for 64 channels of 17.2 mW. This ﬁgure translates into a power budget of 269 µW per channel, in line with published results but allowing a larger transmission distance and more efﬁcient bandwidth occupation of the wireless link. The integrated circuit was mounted on a small and light board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries, the system can continuously work for more than 100 hours allowing for long-lasting neural spike recordings.
There is a growing need for wireless implantable neural recording systems that can simultaneously acquire neural signals from a large number of channels. Recording from hundreds of neurons may allow neurophysiologists to study brain function in freely-behaving animals, and in future will provide the signals necessary to control neural prosthetic devices . Compared to wired systems, wireless neural recording devices provide a number of benefits: reduction of motion artifacts and freedom of animal movements in neuroscience experiments, as well as reduced infection risks and higher patient mobility in neuroprosthetic applications. However, these systems entail severe technical challenges, such as the robustness of the wireless link and the need of a large data transmission band, coupled to low-power dissipation and small size in case of brain-implantable devices. The main issue is related to the huge amount of data associated with a large number of recording channels: in a 64 channel system featuring a 20 kHz sampling frequency (the neural signal band extends to about 7–10 kHz) with 8 bit resolution, the required data rate of the wireless link is 10.24 Mbit/s. Achieving such a high bit rate is not straightforward either in fully implantable devices where power consumption is limited to about 10 mW to avoid tissue necrosis  and in battery-powered systems for maintaining a reasonable battery life. Hence, most integrated circuits (ICs) reported in the literature that simultaneously support neural recording and wireless telemetry must trade-off power consumption against the amount of data to be wirelessly sent.
Data compression was adopted to solve this problem in earlier systems. For example, since in a typical extracellular electrode trace most of the useful information is contained in spikes (or action potentials, APs), Harrison et al.  enable only the transmission of the spike occurrence information, achieving a low bit rate of 330 kbit/s for 100 channels. However, since the examination of the raw traces may improve the selection of the spike detection threshold, the system reported in  allows to collect raw data from 2 out of 64 channels present in the system, while only spike occurrence times are sent for the remaining 62 channels via a 2 Mbit/s wireless link. On the other hand, spike waveforms are used in neuroprosthetic applications to assign spikes to specific neurons improving the prediction of an intended movement . Hence, during the last four years, wireless systems capable of sending all raw data have been reported. In , Chae et al. describe a 128 channel system able to transmit all raw data using an impulse-radio ultra-wide band (IR-UWB) transmitter with up to 90 Mbit/s rate. In such system, problems may arise from skull and skin absorption at high frequencies (signal spectrum is in the 3.5–4.5 GHz range) and from pulse distortion and the need of an external broadband antenna. As a matter of fact, no in vivo tests are reported for this kind of system. In , Ghovanloo et al. report a system that transmits raw data from 32 channels, encoded in a pulse-width modulated (PWM) signal via a 640 kS/s frequency-shift keying (FSK) wireless link. In this system, the transmitted information relies on the time width of each symbol, making this transmission prone to the noise of the wireless link and of the receiver. Moreover, the system in  requires a relatively large bandwidth (38 MHz), which means higher probability of RF interferences, and does not meet the band requirements of any medical communication standard.
We propose here a solution that is intermediate to the two extremes described above. The idea was to employ a data compression algorithm in order to:
preserve the information needed for single neuron identification;
reduce the throughput and thus the power consumption, since the power needed to the antenna is directly proportional to the bit rate ;
keep the bandwidth limited to few MHz, thus reducing the probability of RF interference and verifying the possibility to make in the future the system compliant to Medical Implanted and Communication Service (MICS) or Industrial Scientific and Medical (ISM) bands, in the 402–405 MHz and 902–928 MHz frequency range, respectively.
In particular, having reduced the data rate, it was possible to extend the transmission distance well beyond the 1 m value reported in the above-mentioned works to make possible realistic in vivo experiments with a small penalty in terms of power consumption. The proposed integrated circuit, already presented in , has been included in a complete system, made of a transmission and a receiving unit, that is in use in a neuroscience laboratory on freely-behaving animals in place of commercial wired systems to avoid tethering effects and to provide electrical isolation. In this paper we describes in detail the architecture and circuit design choices, the electrical performance of the IC and the in vivo tests on small-laboratory animals.
The paper is organized as follows. Section 2 describes the overall system made of a signal conditioning and transmitting unit and a receiver built with off-the-shelf components. Section 3 discusses in detail the implementation of the system-on-chip (SoC) building blocks and validates the data compression algorithm by means of ad-hoc simulations, while Section 4 shows the electrical characterization of the integrated circuit and reports the results of in vivo tests on freely-behaving laboratory animals. Finally, a comparison of the implemented SoC with the state-of-the-art is presented in Section 5.
2. System Architecture
The system consists of a wireless recording unit, a receiver built with off-the-shelf modules to maximize its sensitivity plus a remote host complete of a graphical user interface (GUI) to allow neural signal visualization during in vivo experiments.
2.1. Wireless Recording Unit
Figure 1 shows the block diagram of the IC which acts as recording and transmitting module. The circuit consists of 16 low-noise amplifiers (LNAs), which perform low-power and low-noise amplification of neural signals. The amplifier outputs are sampled by a time-division multiplexer (TDM) at 20 kS/s onto one data lead before being further amplified by a variable-gain amplifier (VGA) and converted by an 8 bit successive approximation register (SAR) analog to digital converter (ADC). The digital data are then processed by a logic block, performing data compression, assembly and Manchester encoding of the bit stream. Finally, the digital signal is sent to a 400 MHz binary FSK wireless transmitter based on direct modulation of a Voltage Controlled Oscillator (VCO), enabling a 1.25 Mbit/s data rate. A crystal Clapp oscillator employing an external 20 MHz quartz and a power-on/reset (POR) circuit complete the system, providing a clean 20 MHz frequency clock and a synchronization signal at the start-up. It is worth pointing out that, to reduce silicon area and costs, only 16 amplifiers have been integrated. The remaining 48 channels have been added by connecting a voltage reference to the multiplexer input. In this way all the stages following the amplifier array are designed to process signals from a 64 channel front-end, thus making it possible to reliably assess the actual performance of a complete 64 channel system.
2.2. Receiver and Graphical User Interface
The receiver (see Figure 2) consists of a quadrature zero-IF down-converter (MAX3580) using an LNA with a noise figure of 4.7 dB at 400 MHz, RF and baseband tunable filters and automatic gain control circuits. The quadrature signals are converted by a dual channel, 20 MSps, 10 bit ADC (AD9201) and fed to a Xilinx FPGA module (OpalKelly, XEM3005), which performs frequency demodulation and Manchester decoding and sends the received data to a PC via a USB link. In addition, a Graphical User Interface (GUI) based on Labview/C software was implemented to allow data saving and on-line elaboration.
3. Circuit Design
3.1. Analog Front-End
Amplification and filtering of the input signal are performed by a three-stage circuit shown in Figure 3. The first stage is an AC-coupled high-pass filter, using two MOS-bipolar pseudo-resistors as feedback elements , which enables the synthesis of high-value resistances without using large-area components. The mid-band amplifier gain is given by , set to –67 by taking pF and C2 = 150 fF. The high-pass pole frequency is placed below 10 Hz to reject the offset and the slow voltage drift of the electrode. A tunable GM -C high-pass filter with a cut-off frequency fHP of about 300 Hz is introduced after the first stage. It is designed to reject the low-frequency signals, such as Local Field Potentials (LFPs) in the Hz frequency range that can prevent a correct detection of the neural spikes or even saturate the amplifier, and cuts off the input-referred noise due to the pseudo-resistors of the first amplification stage. After the selective high-pass filter, a second non-inverting gain stage is added to provide further signal amplification and to define the high frequency cut-off, fLP. The stage is a single-ended capacitive-coupled voltage amplifier with a gain , achieved by using pF and fF. A capacitive-coupled structure was preferred to a purely resistive feedback amplifier to minimize the current drawn by the OTA output stage. The DC voltage at the amplifier input is determined by the pseudo-resistor elements in the feedback path, while the low-pass cut-off frequency is set by the gain-bandwidth product of the operational amplifier (GBWP2 ) to about kHz. Note that at very low frequencies this non-inverting stage has a unity gain in order not to amplify the offset of the operational amplifier.
3.1.1. Noise Analysis and First Stage Sizing
In order to minimize the amplifier array power consumption while maintaining the input-referred noise specifications, a rigorous noise analysis of the preamplifier and filter has to be carried out following the approach adopted in . The noise performance of the whole LNA depends on the design of the first-stage OTA, whose input noise power density is mainly determined by a compromise between its thermal and flicker noise. To explain this point, let us denote as Cp the input parasitic capacitance to ground of each input terminals of the first-stage OTA . If we neglect the noise contribution due to the two pseudo-resistors (this term will be addressed in a next step), we can write the input-referred noise of the overall amplifier as:
|Transistor||[mV]||IC||gm [μA/V]||ro [M ]|
To minimize the noise, the first OTA stage has been designed as a simple telescopic cascode amplifier (see Figure 3). This well-known configuration guarantees excellent noise performance thanks to its few transistors, while cascoding and proper transistor sizing ensure enough gain. Straightforward analysis relates the input-referred noise power spectral density to the noise sources of the transistors, leading to:
With regard to the flicker noise, its contribution can be reduced by increasing the PMOS transistor area ( ). Considering that for the adopted technology V2F and 5 fF/μm2 and setting a noise corner frequency lower than 100 Hz, the input PMOS transistors were sized with m2. This sizing results into a stray OTA input capacitance Cp of approximately 500 fF, which does not excessively impair the equivalent input noise. Moreover, in order to fulfill the requirement , the settings m and m were applied, thus forcing these devices to work in the strong inversion region (see Table 1). For this choice of the transistor lengths, cascoding of the input differential pair is needed to not to degrade the output resistance and, thus, to not to lower the amplifier gain. The introduction of Mcas guarantees an output resistance and an amplifier gain dB.
In summary, by careful transistor sizing, the noise within the amplifier band may be reduced to the sole thermal noise. Since in a generic amplifier a trade-off exists between noise and current consumption, its efficiency may be evaluated referring to the noise efficiency factor (NEF ), which is a parameter commonly adopted in literature, proposed in  and defined as:
The transconductance of the input transistors is slightly lower than since their inversion coefficient is larger than zero. For the present design, the input transistor IC is 1.075 (see Table 1), and consequently the rms input noise and the NEF increase by a factor of 1.034.
The input-referred noise of the overall amplifier is larger by a factor than the one of the first operational amplifier, as stated by Equation (1). Taking into account that the parasitic input capacitance is approximately 0.5 pF, mainly due to the OTA input transistors, this factor is equal to 1.065. A further contribution derives from the strays associated with the input capacitor plates that was drastically reduced by connecting the capacitor bottom plate (which has the largest parasitism) to the amplifier input and by connecting the top plate to the OTA terminal. In this way, a parasitic capacitance larger than 1.5 pF was avoided.
The current drawn by the second amplifying stage contributes to the total current in Equation (7) but does not lower the input-referred thermal noise. Therefore, the NEF increases by a factor of , where I1 and I2 are the currents drawn by the first and the second operational amplifier respectively.
Finally, note that the adoption of a telescopic cascode amplifier, known to have a small output dynamic, is not a limiting factor for the input signal amplitude. In fact, the positive voltage swing is mV while the negative swing is about 1 V , thus assuring a maximum amplitude for the input signal of about 7 mV.
3.1.2. Second Amplifying Stage
A second gain stage is needed to increase the amplitude level of the input signal before multiplexing. Since this stage requires a relative large output swing, a two-stages OTA can be employed. Provided that the first stage has enough gain, the impact of this second amplifier on the input-referred noise is negligible, and its power dissipation can be reduced without affecting the noise performance. In fact, the noise of the second op-amp is dominated by the input transistors, designed to operate in weak-inversion region. If we limit the contribution to the equivalent input noise added by the second stage OTA to less than 0.3 (i.e., 1/10 of the dominant contribution), a minimum current of 100 nA is needed in the input differential pair of the second op-amp. To be conservative, we set the bias current to 200 nA in the first stage, while a current of 100 nA is drawn by the second stage.
Finally, nonlinear distortion may be of some concern in the second stage. Distortion arises from the non-linear high-resistance pseudo-resistors placed in the feedback path, which is driven by a large output voltage swing. For this reason the subthreshold MOS transistors were sized to have resistance values an order of magnitude higher than those in the first stage. This choice makes the signal current flowing through them always several orders of magnitudes lower than the signal through the capacitors, limiting the measured Total Harmonic Distortion (THD) generated by the stage below 5% even if the pseudo-resistors were modulated by a 1.5 V peak-to-peak 1 kHz sinusoid.
3.1.3. High-Pass Filter Design and Optimization
Let us now consider the noise due to the MOS-bipolar pseudo-resistors that was neglected in Equation (2). It was experimentally verified that the noise spectral density of the pseudo-resistors complies with the usual equation:
The result suggests to reduce the first term by minimizing the ratio while a large capacitor value CHP is needed to reduce the second term. In practice, the GM cell is a simple differential stage (see Figure 3) whose bias current can be externally tuned. Because a small bias current (I 1 nA) is needed to synthesize a high value resistance, all the transistors work in weak-inversion region and their transconductance is . The current noise of this configuration is therefore:
In summary, in order to keep the input-referred noise due to the first stage pseudo-resistors and to the GM cell in the amplifier band lower than 1 μVrms, f1 has to be at least a factor of 10 smaller than fHP and CHP must be greater than 2 pF. The two pseudo-resistors in the first stage of the circuit in Figure 3 were designed to have Hz (with Hz) and pF.
3.1.4. Line Buffer and Multiplexer
A circular shift register, controlled by a 625 kHz clock (ckmux in Figure 1), sequentially enables each amplifier to access the common data lead; each pass gate switches on both the rising and the falling edge of the multiplexer clock, avoiding clock transitions in the middle of the sampling window. As in this topology each amplifier has to drive a long routing line connecting all the pass-gate outputs, a class-AB buffer is needed to boost the line. To save power, each buffer is switched off when the corresponding amplifier is not selected and turned on when the previous amplifier is selected (i.e., one clock edge before). In this way, at any time, only two buffers are powered, draining about 25 μA each from the supply. Further amplification is provided before sampling by a variable-gain amplifier (VGA) added to the amplification chain at the multiplexer output. The gain can be digitally varied between 1 to 8 by means of two auxiliary control bits.
3.2. Analog to Digital Converter
The multiplexed and amplified signal is then converted into a digital form by an 8 bit SAR ADC (see Figure 1). This topology is well-suited for low power and small-area applications since it requires a minimal amount of analog circuitry. To save area, analog multiplexing of input signals, requiring only one AD converter, was employed even though it resulted in a small power penalty with respect to the use of one converter per each amplifier and digital multiplexing of data .
The number of the converter bits was chosen taking into account the following considerations:
The maximum amplitude for an extra cellular action potential is ~ 1 mV  while the minimum signal is about 10 μV, the latter being determined by the typical input noise due to neural background activity and electrode impedance . Therefore, the ratio between the Full Scale Range (FSR) and the ADC least significant bit, i.e., the dynamic range of the converter, should be better than 1 mV/10 μV 100 . This results in a converter resolution larger than 6.35 bit.
The ADC quantization noise has to be kept much lower than the minimum detectable signal, i.e., the rms input noise. This requirements translates into:
In practice, taking into account that the effective number of bit (ENOB) is always lower than the nominal figure, the use of an 8 bit ADC will provide a safe margin for the design. A higher resolution is useless and harmful since it would increase the ADC power consumption.
The ADC consists of three main parts: the capacitor array, the comparator and the logic block performing the successive-approximation algorithm. The capacitor array, which acts as sampling capacitance during the sampling interval and as charge-sharing DAC during the conversion period, has been implemented as a binary array. The value of the unit capacitance, CLSB, was chosen considering two requirements:
The noise in the sampling phase has to be significantly smaller than the quantization noise. Thus, the total capacitance of the array, CTOT, must satisfy the condition:
The LSB capacitance has to be sufficiently accurate and it has to fulfill the following requirement :
The comparator was implemented as a classical two-stage topology, as depicted in Figure 4. A 20 dB gain preamplifier is followed by a PMOS latch stage and a couple of inverters are connected at the latch outputs to regenerate the signals. The two-stage architecture was preferred to a dynamic latch in order to avoid kickback noise and metastability [20,21].
The successive approximation logic has been implemented as a synchronous full-custom logic. The A/D converter works with a clock frequency of 20 MHz, providing 1.25 MS/s, i.e., about 64 channels kS/s per channel. Hence, a conversion period lasts 16 clock cycles (see Figure 5): The sampling phase lasts 7 clock periods to relax the specs of the input signal buffer, while every bit decision takes one clock period, starting from the most significant bit (MSB ). The last clock cycle is reserved for the end-of-count (EOC) operations. The current consumption of input buffer and A/D converter are 250 and 410 μA, respectively.
3.3. Digital Signal Processing
The implemented data reduction system takes advantage of the low duty cycle of the neural activity to eliminate transmission of useless signal containing only noise. Spike duration and firing rates are typically lower than 1 ms and 100 Hz , respectively. A finite-state machine (FSM in Figure 6) compares each incoming digital sample with a user-programmable digital threshold, i.e., an 8 bit word stored in the embedded SRAM. When the threshold is crossed, 20 samples of the signal from the same channel are recorded, covering a 1 ms time frame (see Figure 7). This strategy was chosen taking into account that a clear identification of APs requires the detection of three features, namely the amplitude of the peak and the trough and the time interval between them , which can be extracted with enough resolution by using 20 samples, even for the fastest spikes. The threshold can be set by the user before the recording starts, choosing among four predefined digital words: “x1000000 ”, “x0100000 ”, “x0010000 ” and “x0001000 ” (corresponding to 1/2, 1/4, 1/8 and 1/16 of half the ADC full scale range). Since the spike can have a first peak either positive or negative and the baseline is at the middle of the ADC range, the threshold is either positive and negative for each sample. For example, considering the first threshold, the FSM is triggered if the incoming sample is larger than “11000000 ” or lower than “01000000 ”. If the gain of the amplification chain is set to the maximum value (83 dB 14000 ), these four thresholds correspond to an input-referred amplitude of ± 54 μV, ± 27 μV, ± 13 μV and ± 7 μV.
The recorded samples are stored in a 2 kbit embedded memory (SRAM in Figure 6) together with the channel address and the timing stamp, both with a 8 bit resolution. Each spike is then compressed in 22 bytes. The SRAM is continuously read at 1 Mbit/s rate by the control logic block, which adds service bits for synchronization at the receiver and then performs Manchester encoding of the bit stream. The final data rate reaching the transmitter is 1.25 Mbit/s. The memory read speed was determined by taking into account two aspects:
the lower the read speed, the higher the compression factor is; 1 Mbit/s read speed results in a compression factor of 10 (from 10.24 Mbit/s, corresponding to 64 channels sampled at 20 kHz per channel and 8 bit per sample, to 1.25 Mbit/s data rate) and allows saving a considerable amount of power and bandwidth at the transmitter side;
considering the worst-case scenario of 64 channels firing at 100 spike/s and 20 samples per spike with an 8 bit resolution, the average data throughput is about 1 Mbit/s.
The memory was sized to reduce missed spikes when burst activity is present. Monte-Carlo simulations were performed considering that the neural firing rate follows a Poisson statistics. Figure 8 shows the missing spike percentage as a function of the average firing rate for each of the 64 channels and for different memory sizes. Opting for 1 Mbit/s read speed and 2 kbit RAM size, the missing spike percentage is less than 0.1% for 64 channels firing at 50 spikes/s and less than 10% for all channels firing at 100 spikes/s. With these choices, the memory is able to store spikes that occur in the same 1 ms frame in 11 consecutive channels before missing a spike. Each AP is transmitted, once completely stored, in 176 μs and thus the worst-case latency time (time difference between the detection and the transmission of an AP) is about 2.9 ms, which is not an issue both in neuroscience experiments and in future prosthetic applications .
The validity of the data-reduction algorithm was tested by running a custom clustering software that employed fuzzy c-means spike sorter [24,25] on a data set from a public source  with spike waveforms hardly distinguishable one from each other (see Figure 9). The ratio between the peak-to-peak spike amplitude and the rms noise was approximately 10 . Clustering based on Principal Component Analysis (PCA) was performed on original data containing spikes from three different neurons and on the same data but reduced according to the above windowing strategy. Figure 9 shows that clustering on the reduced data set leads to clear separation of the three spike families, with identification errors reported in Table 2. Two types of error occur in a PCA-based clustering: type I errors occur when APs from two different neurons are grouped together (false positives), whilst type II errors occur when not all APs generated by one neuron are grouped together (false negatives). When applied to the original dataset, the PCA-based identification procedure leads to type I/type II mean error rates of 4.1%–5.2%, respectively. The reduced data sets showed 4.6%–5.3% values, thus demonstrating that the reduction strategy preserves the quality needed for effective neuron identification. These results are not surprising considering that, as stated in , more than 80% of neural spike information is carried by three analog features of the AP waveform, namely the peak and the through amplitudes and the time between them. The results of spike sorting using these analog features  and performed on the same trace are also reported in Table 2. Note that the compression method employed in this work always outperforms the clustering obtained using only these three features. Finally, it is worth nothing that the current consumption of the overall digital signal processing is limited to about 400 μA, most of which consumed by the finite-state machine.
3.4. Manchester-Coded FSK Modulator
The 1.25 Mbit/s bit stream is transmitted using a Manchester-coded binary Frequency Shift Keying (MC-2FSK) modulation at a carrier frequency of 400 MHz. The transmitter (see Figure 10) consists of a voltage-controlled oscillator (VCO) directly modulated by the digital data, inserted in a Phased-Locked Loop (PLL). Since the modulator is a power-hungry system, the design of the whole PLL, and in particular of the high-frequency oscillator, has to be carried out with great care.
The oscillator has a current-biased topology with double cross-coupled pair transconductor. This oscillator architecture allows to minimize the current consumption for a given phase noise with respect to the topology featuring a single differential pair transconductor . In order to accurately set the PLL output frequency at the desired value of 400 MHz and to compensate for process, temperature and power-supply variations, the oscillator has to span over ±10% of its central frequency, i.e., a band of about ±40 MHz. This means that the capacitance has to be varied as:
Once the tank parameters have been determined, the current IBIAS of the tail generator and the (W/L) ratio of the pair transistors have to be chosen taking into account the following considerations:
The small-signal loop gain or excess gain  of the oscillator (gmRTANK, where gm is the small-signal transconductance of the double differential-pair and RTANK is the tank equivalent parallel resistance) has to be larger than 1 in order to assure the oscillation start-up. Since the common-mode output voltage of the oscillator is set to the half of the power supply to maximize the oscillation swing, i.e., V, we have:
The differential oscillation amplitude, A0, has to be sufficiently large ( 1.5 V) to drive the subsequent stages, i.e., the frequency dividers and the power amplify. Since
The VCO phase noise, which mainly determines the phase noise of the whole synthesizer at a frequency offset larger than the PLL loop bandwidth, has to be sufficiently lower in order not to worsen the Signal-to-Noise-Ratio (SNR ) of the modulated signal. This can be evaluated as Single-Sideband to Carrier Ratio, i.e., as the ratio of the power in a 1 Hz bandwidth at an offset from the fundamental angular frequency and the power of the carrier, giving :
A resonant filter (at twice the oscillation frequency) connected to the source of the NMOS differential pair transistors (see Figure 10 and Figure 11) can be added to reduce flicker noise up-conversion into phase noise, which can severely limit the VCO performance .
For μA, C in the 6–11 pF range and , the excess gain is approximately 2 and the oscillation amplitude is larger than 2 V, preventing the tail current generator to enter the ohmic region and avoiding a phase noise degradation. Moreover, these choices ensure that the phase noise is not an issue being better than 1–50 dBc/Hz at 1 MHz frequency offset.
The VCO is followed by a cascade of a divide-by-2 dynamic logic prescaler and a static modulo-10 CMOS counter, which further divides the frequency by 10 . The PLL reference is the same 20 MHz master clock, allowing the loop to set the oscillation frequency at 20 times the reference clock, i.e., 400 MHz. The PLL also includes a phase-frequency detector with a charge-pump driving an RC -C off-chip filter (see Figure 10), which sets the loop bandwidth to 50 kHz. Excluding the VCO, the power consumption is mainly due to the high-frequency prescaler, which draws more than 200 μA. The current consumption of the whole synthesizer is about 700 μA.
The synthesizer frequency is modulated in an open-loop mode by the data at 1.25 MHz, i.e., at 1.25 Mbit/s rate with Manchester encoding. Thus, the loop is open for the frequency modulation since the PLL bandwidth is significantly lower than the bit-rate. This prevents the PLL to filter out the induced frequency modulation. The only purpose of the loop is to fix the central oscillation frequency in order to avoid frequency drift due to temperature and power supply variations. To limit the occupied bandwidth, a frequency deviation of about ±400 kHz was adopted. Considering a modulation frequency of 1.25 MHz, this value corresponds to a modulation index of 0.64. The bandwidth of the transmitted signal is determined by the Carson rule :
3.5. Power Amplifier
The transmitter is completed by a class-AB power amplifier (PA) that drives a 50- antenna via an off-chip resonant filter. The PA consists of an open-drain PMOS transistor directly connected to the oscillator output, sized in order to draw about 3.5 mA. Thus, the power delivered to the antenna is about 0 dBm considering a reasonable efficiency of 10%. The output power, and thus the power consumption of the PA, were set after estimating the sensitivity of the receiver, which depends on the modulation type, the signal bandwidth and the noise factor of the receiver itself. The receiver input noise in the signal bandwidth of 3 MHz is:
4. Experimental Results
4.1. Electrical Characterization
The chip was fabricated in AMS 0.35 μm, 3 V 4M2P CMOS process and occupies a total area of mm2, pads included (see Figure 11). The preamplifier has a mid-band gain of about 65 dB, a high frequency cut-off of 10.5 kHz and a low-frequency cut-off tunable from 1 Hz to 1 kHz (see Figure 12). The input-referred noise, for Hz, is 3.05 μV, while the current consumption is 4 μA for the first stage, 0.001 μA and 0.3 μA for the high-pass filter and the second amplifying stage respectively, resulting in an overall NEF of 2.5. The input-referred power spectral density is shown in Figure 13 for different values of the GM -C filter high-pass corner frequency. The plateau of –152 dBV2 /Hz corresponds to an input-referred noise of about (25 nV)2 /Hz, close to the expected value. Note that, for Hz, the input-referred noise is mainly due to the GM -C high-pass filter, as predicted by Equation (14). The common-mode rejection ratio (CMRR ) and the power supply rejection ratio (PSRR ) of the overall pre-amplifier are higher than 65 dB and 50 dB, respectively, while the cross-talk between adjacent channels due to the analog multiplexing is lower than –40 dB.
With regard to the AD converter, Figure 14 shows the results of static measurements. The converter features a DNL less than 0.45 LSB and an INL less than 1 LSB. Figure 15 shows the output spectrum of the ADC for a full-scale sine wave at 1 kHz frequency as input signal. The signal to noise plus distortion ratio (SNDR) is close to 45 dB, and the number of effective bit (ENOB) is thus about 7.2.
Considering the modulator, the frequency range covered by the VCO spans from 310 to 460 MHz (see Figure 16), allowing to lock the PLL loop to a frequency of 400 MHz frequency even with a large spread of tank component values and for sizable variations in power supply and temperature. When no data modulation is performed, the modulator phase noise (see Figure 17) is less than –123 dBc/Hz at 1 MHz offset from the carrier. The phase noise spectrum has a typical low-pass shape, with 50 kHz cut-off frequency, since it is completely dominated by the charge-pump noise , while the VCO phase noise is much lower. The rms integral frequency noise of the modulator in the 10 Hz to 10 kHz band is less than 3 kHz (see the residual frequency FM in Figure 17), whereas the output spectrum of the synthesizer when acting as frequency modulator is depicted in Figure 18: more than 98% of the signal power is included in a 3 MHz band.
For a whip antenna at the transmitter and a dipole antenna at the receiver side, the received power in a free space is shown in Figure 19. The sensitivity of the receiver has been measured to be –74 dBm for a BER of , close to the estimated theoretical value predicted by Equation (27) of –79 dBm, allowing a transmission range larger than 30 m. The system has also been successfully tested for a 10 m distance between transmitter and receiver in a hostile environment as a neuroscience laboratory, giving a PA efficiency of about 7% while delivering a –2 dBm at a 50- output load. Disabling the PA, the tank inductor may act as transmitting antenna; in such measurements about –70 dBm was received by a loop antenna placed at approximately 5 cm from the tank inductor.
The overall performance of the implemented system is provided in Table 3. The power consumption of the presented circuit has been computed by projecting the performance to a complete 64 channel system. To this end, the additional budget needed for the missing 48 amplifiers has been added to the actual power consumption (16.6 mW) leading to 17.2 mW (6.7 mW with the PA turned off). The estimate is fair since all the other circuit blocks work with the same data rate of a full 64 channel system.
|Technology||0.35 μm AMS|
|Supply Voltage||3 V|
|Number of channels||64 (16 available)|
|Pre-amplifier gain||65 dB|
|Pre-amplifier band||HP tunable-10.5 kHz|
|ADC DNL-INL||LSB; LSB|
|Transmission frequency||400 MHz|
|20-MHz crystal oscillator||90 μA|
|ADC buffer||250 μA|
|DSP+2 kbit RAM||400 μA|
|Modulator (PLL)||700 μA|
|Power amplifier||3.5 mA|
|Total power consumption||6.7 mW (17.2 mW with PA enabled)|
4.2. In Vivo Experiments
Figure 20 shows the system mounted on a rat for in vivo signal acquisition. It consists of two parts, a wireless neural recording headstage and a backpack. To limit disturbances collected from the environment, a small board ( cm2 and 4.5 g of weight) is directly connected to a 16 channel microelectrode array (Tucker-Davis), with an impedance in the 20–60 k range at 1 kHz, implanted into the somatosensory cortex of an adult rat. The board includes the packaged chip and 10 external small surface-mount components (0805 or 0603 footprint): the VCO inductor, the power-amplifier resonant filter components (2 capacitors and 1 inductor), the 20 MHz quartz, the PLL loop-filter (1 resistor and 2 capacitors) and 2 decoupling capacitors between power supplies. The antenna is a quarter-wavelength whip antenna: it consists of a piece of wire about 17 cm long, easily placed along the back of the rat. The backpack has a weight of 40 g and includes two AAA batteries with 1000 mA/h capacity that may allow neural activity recordings for more than 100 hours. The two batteries are connected via three 10 cm long wires to the headstage. At the beginning of the in vivo experiment, the quality of the signals from the implanted electrodes was analyzed using a commercial acquisition system by recording the raw signals and noise from the same 16 electrode channels. The recorded traces featured a noise of about 10 μVrms on all channels. The threshold of the digital peak processor was set to “x1000000 ” and the gain of the overall amplifying chain to the maximum value (83 dB) since the peak-to-peak spike amplitude was always lower than 100 μV. Thus, the digital threshold corresponds to an input-referred amplitude of about ±30 μV, i.e., ±3 times the rms noise. The high-pass cut-off frequency of the front-end amplifiers was set to about 300 Hz to properly reject the low-frequency signals and the power-line noise, enabling correct spike detection. The receiver dipole antenna has been placed at two meters from the rat while neural activity was recorded. Figure 21 shows a single trace recorded during the experiment and two spike waveforms extracted from the data stream, while in Figure 22 a large number of spikes recorded on the same channel are shown aligned in time.
5. Discussion and Conclusions
Table 4 compares the implemented system to other wireless neural recording ICs with respect to the three most important features, i.e., the transmitted data type (raw data, spike detection or spike waveform), the transmission range and the power consumption per channel. For a fair comparison, since state-of-the-art wireless neural recording systems feature a transmission range always lower than 1 m, the proposed circuit can be thought sized to get a similar transmission range. Since the power needed at the antenna is inversely proportional to the square of the transmission distance, the PA power consumption could be scaled down by a factor of 900, i.e., (30 m/1 m)2. In this case the equivalent power consumption of the whole system reduces to about 6.7 mW, corresponding to less than 105 μW per channel.
|Technology||0.5 μm||0.35 μm||0.5 μm||0.13 μm||0.35 μm|
|Power source||inductive link||battery||battery||NA||battery|
|Number of channels||100||128||32||64||64 (16 avail.)|
|Overall gain||60 dB||57–60 dB||68–78 dB||54–60 dB||65–83 dB|
|Input noise||5.1 μV||4.9 μV||9.3 μV||6.5 μV||3.05 μV|
|TX frequency||433 MHz||4 GHz||915 MHz||915 MHz||400 MHz|
|Data type||spike detection||raw data||raw data||raw data||AP waveform|
|Data rate||330 kbit/s||90 Mbit/s||640 kbaud/s||1.5 Mbit/s||1.25 Mbit/s|
|Bandwidth||0.8 MHz||1 GHz||38 MHz||3 MHz||3 MHz|
|TX range||13 cm||1 m||1m||1 m||30 m|
|Power per channel||135 μW/ch||47 μW/ch||220 μW/ch||80 μW/ch||269 μW/ch|
By comparing our system with the one described in , working in the same frequency range, the proposed system features a lower power consumption per channel. Also the data quality is greatly improved since spike detection is replaced by waveform detection, making possible single spike identification over a large microelectrode array. Compared with the IC in , our system shows an improvement of a factor larger than 2 in terms of power consumption per channel. It is true that the data rate does not allow all raw data acquisition as in , but our design optimizes information transfer and is potentially compliant with the narrowband spectral limitations in the Medical Implant Communication Service (MICS ) band range (402–405 MHz). In the future, this system could also be designed to work in the Industrial Scientific and Medical (ISM ) band (902–928 MHz).
The system in  is better in term of power per channel but, relying on an UWB transmitter, it can suffer from interference. Moreover, this system has never been tested in in vivo experiments and no information on the adopted antenna or on the power delivered by the PA is given. Regarding the system presented in , its power consumption per channel (80 μW/ch) was evaluated considering the minimum transmitter power, assuming that it allows a 1 m transmission distance. However, the data rate is limited to 1.5 Mbit/s, translating into data acquisition at a sampling rate 3 kS/s from all 64 channels. Higher sampling rates are possible only for a limited number of channels: assuming that 20 kS/s is the minimum sampling rate to acquire good quality neural signals, the maximum number of channels that can be recorded and transmitted simultaneously is only 9.
In conclusion, thanks to the implemented compression algorithm that allows to preserve the information needed for single neuron identification while limiting the data throughput and the bandwidth, we achieved a good balance between power consumption and quality of transmitted data and transmission range. In addition, the power consumption per channel was lowered by a careful sizing of each individual circuit block.
The authors would like to thank L. Fadiga (IIT, Genova) for useful discussions and A. Oleynjk (Universita’ di Ferrara) for providing us the clustering software.
References and Notes
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