J. Low Power Electron. Appl. 2012, 2(2), 143-154; doi:10.3390/jlpea2020143
Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN
1
The Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA
2
SPARC Core Memory Group, Oracle Corporation, Santa Clara, CA 95054, USA
*
Author to whom correspondence should be addressed.
Received: 16 February 2012 / Revised: 6 April 2012 / Accepted: 11 April 2012 / Published: 18 April 2012
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
Abstract
The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write VMIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4–13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the unassisted test case. View Full-TextKeywords:
sub-threshold circuits, low power SRAM; SRAM assist methods; alternative bitcell topologies
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).
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Boley, J.; Wang, J.; Calhoun, B.H. Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN. J. Low Power Electron. Appl. 2012, 2, 143-154.
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J. Low Power Electron. Appl.
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