J. Low Power Electron. Appl. 2012, 2(2), 155-167; doi:10.3390/jlpea2020155
Article

0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process

Piotr Olejarz 1 email, Kyoungchul Park 2 email, Samuel MacNaughton 2 email, Mehmet R. Dokmeci 3 email and Sameer Sonkusale 2,* email
1 Electrical and Computer Engineering, Northeastern University, Boston, MA 02155, USA 2 NanoLab, Electrical and Computer Engineering, Tufts University, Medford, MA 02155, USA 3 Center for Biomedical Engineering, Department of Medicine, Brigham and Women’s Hospital, Harvard Medical School, Boston, MA 02115, USA
* Author to whom correspondence should be addressed.
Received: 15 March 2012; in revised form: 8 May 2012 / Accepted: 8 May 2012 / Published: 18 May 2012
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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Abstract: We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design.
Keywords: sub-threshold; weak inversion; analog design; OTA; low power; FDSOI

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Cite This Article

MDPI and ACS Style

Olejarz, P.; Park, K.; MacNaughton, S.; Dokmeci, M.R.; Sonkusale, S. 0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process. J. Low Power Electron. Appl. 2012, 2, 155-167.

AMA Style

Olejarz P, Park K, MacNaughton S, Dokmeci MR, Sonkusale S. 0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process. Journal of Low Power Electronics and Applications. 2012; 2(2):155-167.

Chicago/Turabian Style

Olejarz, Piotr; Park, Kyoungchul; MacNaughton, Samuel; Dokmeci, Mehmet R.; Sonkusale, Sameer. 2012. "0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process." J. Low Power Electron. Appl. 2, no. 2: 155-167.

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