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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (30 June 2022) | Viewed by 25776

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Dr. Athanasios Kakarountas

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Department of Computer Science and Biomedical Informatics, University of Thessaly, 35131 Lamia, Greece
Interests: computer and embedded systems architecture; VLSI circuits & systems design; low-power design and/or design-for-test; design of hardware accelerators for a variety of applications (e.g. image processing, cryptography, medical devices etc.)
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Special Issue Information

Dear Colleagues,

The focus of this Special Issue is on the research challenges related to the design of emerging microelectronics and VLSI circuits and systems that meet the demanding specifications of innovative applications. This Special Issue considers challenges in the fields of low power consumption, small integration area, testing and security, without, however, being limited to them. Authors are encouraged to submit works related to emerging research topics and applications, such as hardware security, low-power IoT devices, high-performance processing cores, etc.

The topics of interest include, but are not limited to:

Device modeling
Emerging technologies
CAD for VLSI design
Hardware/software co-design
Testing and verification
FPGA-based design
Embedded systems
IP cores
Low-power circuits and systems
Hardware security
Emerging applications
VLSI for AI and ML algorithms

Dr. Athanasios Kakarountas
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (11 papers)

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Research

20 pages, 772 KiB

Open AccessFeature PaperArticle

Adaptive BIST for Concurrent On-Line Testing on Combinational Circuits

by Vasileios Chioktour and Athanasios Kakarountas

Electronics 2022, 11(19), 3193; https://doi.org/10.3390/electronics11193193 - 5 Oct 2022

Viewed by 1241

Abstract

Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design issues causing the degradation of totally self-checking (TSC) property, which is proved to be fatal for further operations (e.g., space electronics, medical devices). In addition to the exploration of the degradation of TSC property over time, a concurrent on-line testing architecture is offered that adjusts the input activity, addressing the absence of input values or the low frequency of their appearance (e.g., during sleep mode). During concurrent on-line testing, the inputs of the circuit under test (CUT) are, at the same time, its test vectors. This architecture tolerates possible degradation of the terms that contribute to the calculation of the totally self-checking goal (TSCG

(t)

). An adaptive built-in self-test (BIST) unit is proposed that dynamically applies test vector subsets when permitted, based on the frequency of appearance of the input values. The clustering of the inputs is based on the k-means algorithm and, in combination with the ordering of the test vectors to minimize the subsets, results in partitioning the test procedure in a significantly shorter time. The comparison to other solutions used for concurrent on-line testing showed that the proposed adaptive BIST has significant advantages. It can cope with rare occurrences, or even no occurrence, of input values by enabling the BIST mechanism appropriately. The results showed that it may increase the TSCG

(t)

up to almost 90% when applied during a low-power mode and present better concurrent test latency (CTL) when assumptions regarding the availability of all input values and the probability of occurrence are not realistic. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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16 pages, 14149 KiB

Open AccessArticle

Design of Light-Weight Timing Error Detection and Correction Circuits for Energy-Efficient Near-Threshold Voltage Operation

by Xuemei Fan, Hao Liu, Hongwei Li, Shengli Lu and Jie Han

Electronics 2022, 11(18), 2879; https://doi.org/10.3390/electronics11182879 - 11 Sep 2022

Cited by 1 | Viewed by 1805

Abstract

Near-threshold voltage (NTV) operation has the potential to improve the energy efficiency of digital integrated circuits. However, the use of a conservative timing guard band to avoid the timing errors introduces excessive timing margins, thus causing larger energy dissipation in the NTV region. An error-tolerant design based on timing error detection and correction circuits has been shown to be a promising solution to mitigate these issues. This paper presents a light-weight timing error-tolerant flip-flop (ETFF) design. This design detects timing errors using a node transition signal detector with only nine transistors and corrects these errors during the same clock cycle. Moreover, transistor sizing is explored to optimize the trade-off between performance and area overhead. The proposed ETFFs are inserted into a monitored circuit by replacing original flip-flops at timing-monitored points. To further reduce the overhead, we develop a mean-time-to-failure-aware method to select the monitored points by simultaneously considering the critical path coverage and activation rates of flip-flops. The simulation results show that a CNN accelerator using the proposed timing error-tolerant design implemented in the SMIC CMOS 40 nm process can robustly work at 1.1–0.3 V with only 3.5% area overhead. Furthermore, this design reduces the area overhead by 54.68% and improves the energy efficiency by 53.69% at 0.6 V, compared with the Razor flip-flop design. The advantage of the proposed design lies in that it requires smaller circuit overheads and can work reliably in a wider range of supply voltages. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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12 pages, 344 KiB

Open AccessArticle

A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

by Xiqin Tang, Yang Li, Chenxiao Lin and Delong Shang

Electronics 2022, 11(17), 2685; https://doi.org/10.3390/electronics11172685 - 27 Aug 2022

Viewed by 1675

Abstract

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b]. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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15 pages, 1219 KiB

Open AccessArticle

An Extended Instruction Set for Bioinformatics’ Multiple Sequence Alignment

by Anargyros Gkogkidis, Vasileios Tsoukas and Athanasios Kakarountas

Electronics 2022, 11(16), 2550; https://doi.org/10.3390/electronics11162550 - 15 Aug 2022

Cited by 2 | Viewed by 1530

Abstract

Multiple Sequence Alignment (MSA) is one of the most fundamental methodologies in Bioinformatics and the method capable of arranging DNA or protein sequences to detect regions of similarity. Even on cutting-edge workstations, the MSA procedure requires a significant amount of time regarding its execution time. This paper demonstrates how to utilize Extensa Explorer by Tensilica (Cadence) to create an extended instruction set to meet the requirements of some of the most widely used algorithms in Bioinformatics for MSA analysis. Kalign showed the highest acceleration, reducing Instruction Fetches (IF) and Execution Time (ET) by 30.29 and 43.49 percent, respectively. Clustal had acceleration of 14.2% in IF and 17.9% in ET, whereas Blast had 12.35% in IF and 16.25% in ET. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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21 pages, 5633 KiB

Open AccessArticle

Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending

by Tanya Mendez, Subramanya G. Nayak, Vasanth Kumar P., Vijay S. R. and Vishnumurthy Kedlaya K.

Electronics 2022, 11(15), 2461; https://doi.org/10.3390/electronics11152461 - 8 Aug 2022

Cited by 4 | Viewed by 1675

Abstract

The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain optimization in power and delay, conventional CSLA is refined by substituting ripple carry adders (RCA) with the newly proposed selector unit to minimize the switching activity. The research work includes the power, area, and delay estimates of the design from synthesis using the gpdk-90 nm and gpdk-45 nm standard cell libraries. The proposed adders exhibit reduced delay, power dissipation, area, power delay product (PDP), energy delay product (EDP), and area delay product (ADP) compared to the existing approximate adders. The proposed adder is used in an image blending application. There is a significant improvement in the peak-signal-to-noise ratio (PSNR) in the blended image compared to the standard designs. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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13 pages, 3548 KiB

Open AccessArticle

Single-Branch Wide-Swing-Cascode Subthreshold GaN Monolithic Voltage Reference

by Cesare Bimbi, Salvatore Pennisi, Salvatore Privitera and Francesco Pulvirenti

Electronics 2022, 11(12), 1840; https://doi.org/10.3390/electronics11121840 - 9 Jun 2022

Cited by 1 | Viewed by 1560

Abstract

A voltage reference generator in GaN IC technology for smart power applications is described, analyzed, and simulated. A straightforward design procedure is also highlighted. Compared to previous low-power monolithic solutions, the proposed one is based on a single branch and on transistors operating in a subthreshold. The circuit provides a nearly 2.7 V reference voltage under 4 V to 24 V supply at room temperature and with typical transistor models. The circuit exhibits a good robustness against large process variations and improves line regulation (0.105 %V) together with a reduction in area occupation (0.05 mm²), with a reduced current consumption of 2.7 µA (5 µA) in the typical (worst) case, independent of supply. The untrimmed temperature coefficient is 200 ppm/°C. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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15 pages, 4004 KiB

Open AccessArticle

Machine-Learning-Based Multi-Corner Timing Prediction for Faster Timing Closure

by Zhenyu Zhao, Shuzheng Zhang, Guoqiang Liu, Chaochao Feng, Tianhao Yang, Ao Han and Lei Wang

Electronics 2022, 11(10), 1571; https://doi.org/10.3390/electronics11101571 - 13 May 2022

Cited by 3 | Viewed by 3259

Abstract

For the purpose of fixing timing violations, static timing analysis (STA) of full-corners is repeatedly executed, which is time-consuming. Given a timing path, timing results at some corners (“dominant corners”) are utilized to predict timing at other corners (“non-dominant corners”), which can greatly shorten the runtime of STA. However, the huge number of combinations of the dominant corners and the wide difference in prediction accuracy make it difficult to apply multi-corner timing prediction to chip industrial design. In this paper, we propose a dominant corner selection strategy to quickly determine the dominant corner combination with high prediction accuracy, along with which a new multi-corner timing prediction process is established to speed up STA. Experimental results show that our method can not only effectively accelerate STA, but also ensure the high prediction accuracy of the prediction timing. On the public ITC’99 benchmark, the prediction accuracy of the dominant corner combination selected by the proposed method is up to 98.2%, which is an improvement of 15% compared to the state-of-the-art method. For industrial application, we apply our method by using timing results on only 2 dominant corners to predict the other 12 non-dominant corners, which accelerates the runtime of the timing closure process by more than 2×. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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13 pages, 13345 KiB

Open AccessArticle

An Effective Clustering Algorithm for the Low-Quality Image of Integrated Circuits via High-Frequency Texture Components Extraction

by Zexiao Liang, Guoliang Tan, Chen Sun, Jianzhong Li, Lijun Zhang, Xiaoming Xiong and Yuan Liu

Electronics 2022, 11(4), 572; https://doi.org/10.3390/electronics11040572 - 14 Feb 2022

Cited by 2 | Viewed by 1414

Abstract

Verification is one of the core steps in integrated circuits (ICs) manufacturing due to the multifarious defects and malicious hardware Trojans (HTs). In most cases, the effectiveness of the detection relies on the quality of the sample images of ICs. However, the high-precision and noiseless images are hard to capture due to the mechanical precision, manual error and environmental interference. In this paper, an effective approach for processing the low-quality image data of ICs is proposed. Our approach can successfully categorize the partial pictures of multiple objected ICs with low resolution and various noise. The proposed approach extracts the high-frequency texture components (HFTC) of the images and constructs a graph with the correlationship among features. Subsequently, the spectral clustering is conducted for obtaining the final cluster indicators. The low-quality images of ICs can be successfully categorized by the proposed approach, which will provide a data foundation for the following verification tasks. In order to evaluate the effectiveness of the proposed approach, several experiments are conducted in the simulated datasets, which are generated by corrupting the real-world data in different conditions. The clustering results reveal that our approach can achieve the best performance with good stability compared to the baselines. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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12 pages, 1685 KiB

Open AccessFeature PaperArticle

Hardware Implementation Study of Particle Tracking Algorithm on FPGAs

by Alessandro Gabrielli, Fabrizio Alfonsi, Alberto Annovi, Alessandra Camplani and Alessandro Cerri

Electronics 2021, 10(20), 2546; https://doi.org/10.3390/electronics10202546 - 18 Oct 2021

Cited by 4 | Viewed by 2158

Abstract

In recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are even more relevant. This paper shows an example of FPGA hardware implementation, via a firmware design, of a complex analytical algorithm: The Hough transform. This is a mathematical spatial transformation used here to facilitate on-the-fly recognition of the trajectories of ionising particles as they pass through the so-called tracker apparatus within high-energy physics detectors. This is a general study to demonstrate that this technique is not only implementable via software-based systems, but can also be exploited using consumer hardware devices. In this context the latter are known as hardware accelerators. In this article in particular, the Xilinx UltraScale+ FPGA is investigated as it belongs to one of the frontier family devices on the market. These FPGAs make it possible to reach high-speed clock frequencies at the expense of acceptable energy consumption thanks to the 14 nm technological node used by the vendor. These devices feature a huge number of gates, high-bandwidth memories, transceivers and other high-performance electronics in a single chip, enabling the design of large, complex and scalable architectures. In particular the Xilinx Alveo U250 has been investigated. A target frequency of 250 MHz and a total latency of 30 clock periods have been achieved using only the 17 ÷ 53% of LUTs, the 8 ÷ 12% of DSPs, the 1 ÷ 3% of Block Rams and a Flip Flop occupancy range of 9 ÷ 28%. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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21 pages, 2740 KiB

Open AccessFeature PaperArticle

Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

by Lorenzo Benvenuti, Alessandro Catania, Giuseppe Manfredini, Andrea Ria, Massimo Piotto and Paolo Bruschi

Electronics 2021, 10(10), 1156; https://doi.org/10.3390/electronics10101156 - 13 May 2021

Cited by 5 | Viewed by 3365

Abstract

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage

Δ Σ

modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based

Δ Σ

modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence^TM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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17 pages, 9276 KiB

Open AccessArticle

Design of Multi Standard Near Field Communication Outphasing Transmitter with Modulation Wave Shaping

by Žiga Korošak, Nejc Suhadolnik and Anton Pleteršek

Electronics 2021, 10(2), 188; https://doi.org/10.3390/electronics10020188 - 15 Jan 2021

Viewed by 1876

Abstract

The aim of this work is to tackle the problem of modulation wave shaping in the field of near field communication (NFC) radio frequency identification (RFID). For this purpose, a high-efficiency transmitter circuit was developed to comply with the strict requirements of the newest EMVCo and NFC Forum specifications for pulse shapes. The proposed circuit uses an outphasing modulator that is based on a digital-to-time converter (DTC). The DTC based outphasing modulator supports amplitude shift keying (ASK) modulation, operates at four times the 13.56 MHz carrier frequency and is made fully differential in order to remove the parasitic phase modulation components. The accompanying transmitter logic includes lookup tables with programmable modulation pulse wave shapes. The modulator solution uses a 64-cell tapped current controlled fully differential delay locked loop (DLL), which produces a 360° delay at 54.24 MHz, and a glitch-free multiplexor to select the individual taps. The outphased output from the modulator is mixed to create an RF pulse width modulated (PWM) output, which drives the antenna. Additionally, this implementation is fully compatible with D-class amplifiers enabling high efficiency. A test circuit of the proposed differential multi-standard reader’s transmitter was simulated in 40 nm CMOS technology. Stricter pulse shape requirements were easily satisfied, while achieving an output linearity of 0.2 bits and maximum power consumption under 7.5 mW. Full article

(This article belongs to the Special Issue VLSI Circuits & Systems Design)

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