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J. Low Power Electron. Appl. 2011, 1(3), 334-356; doi:10.3390/jlpea1030334
Article

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

1,* , 2
, 1
, 1
, 1
, 1
 and 2
1 Oregon State University, 1148 Kelley Engineering Center, Corvallis, OR 97333, USA 2 University of Texas at Austin, 1 University Station, C0803 ENS Building, Austin, TX 78712, USA
This research was funded in part by the US Government. The views and conclusions contained in thisdocument are those of the authors and should not be interpreted as representing the official policies,either expressed or implied, of the US Government.
* Author to whom correspondence should be addressed.
Received: 20 May 2011 / Revised: 29 September 2011 / Accepted: 29 September 2011 / Published: 11 October 2011
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
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Abstract

While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.
Keywords: variation tolerance; error detection; error recovery variation tolerance; error detection; error recovery
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Crop, J.; Krimer, E.; Moezzi-Madani, N.; Pawlowski, R.; Ruggeri, T.; Chiang, P.; Erez, M. Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review. J. Low Power Electron. Appl. 2011, 1, 334-356.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert