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J. Low Power Electron. Appl. 2011, 1(3), 334-356; doi:10.3390/jlpea1030334
Article

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

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Received: 20 May 2011; in revised form: 29 September 2011 / Accepted: 29 September 2011 / Published: 11 October 2011
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
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Abstract: While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.
Keywords: variation tolerance; error detection; error recovery variation tolerance; error detection; error recovery
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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MDPI and ACS Style

Crop, J.; Krimer, E.; Moezzi-Madani, N.; Pawlowski, R.; Ruggeri, T.; Chiang, P.; Erez, M. Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review. J. Low Power Electron. Appl. 2011, 1, 334-356.

AMA Style

Crop J, Krimer E, Moezzi-Madani N, Pawlowski R, Ruggeri T, Chiang P, Erez M. Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review. Journal of Low Power Electronics and Applications. 2011; 1(3):334-356.

Chicago/Turabian Style

Crop, Joseph; Krimer, Evgeni; Moezzi-Madani, Nariman; Pawlowski, Robert; Ruggeri, Thomas; Chiang, Patrick; Erez, Mattan. 2011. "Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review." J. Low Power Electron. Appl. 1, no. 3: 334-356.


J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert