A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM
Abstract
:1. Introduction
2. Time-Domain PWM DPS
2.1. Conventional Architecture
2.2. Conversion Time Analysis
2.2.1. Uniform Time-Domain Quantization
2.2.2. Non-Uniform Time-Domain Quantization
3. The Proposed Multi-Reset Integration (MRI) Scheme
3.1. MRI Concept
3.2. Trade-off Analysis
4. MRI-Based Digital Pixel Sensor
4.1. Overall Architecture
4.2. Pixel Circuit
4.3. 2T DRAM Implementation
4.4. Differential Sensing Scheme and Voltage Generation
4.5. Read and Refresh Circuit
5. Power Analysis and Power Reduction Techniques
5.1. Power Consumption Analysis
5.2. Power Reduction Techniques
6. Hardware and Measurement Results
7. Conclusions
Supplementary Material
jlpea-01-00077-s001.pdfAverage Power at 30 f/s | Average Energy per Frame at 30 f/s | |
---|---|---|
Array (Pixels) | 13.9 mW | 13.9 μJ (3.4 nJ/pixel) |
Scan shift register | 800 nW | 23 nJ |
Write buffers | 24 μW | 24 nJ |
Scan register for line selection | 10 nW | 0.3 nJ |
Precharge and sense amplifiers | 430 nW | 13 nJ |
This Work | [7] | [2] (Conventional) | [4] | |
---|---|---|---|---|
Technology | 0.35 μm | 0.35 μm | 0.35 μm | 0.35 μm |
Supply voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
Pixel area | 22 μm × 22 μm | 30 μm × 26 μm | 45 μm × 45μm | 50 μm × 50 μm |
Fill factor | 20% | 16% | 12% | 20% |
Pixel current | 1 μA | N/A | 1.6 μA | N/A |
Transistor count | 25 | 32 | 91 | 38 |
Resolution | 4/8 bits | 4/8 bits | 8 bits | 4/8 bits |
Frame/second | 33 | 300 | 33 * | 33 * |
Acknowledgments
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Zhang, X.; Leomant, S.; Lau, K.L.; Bermak, A. A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM. J. Low Power Electron. Appl. 2011, 1, 77-96. https://doi.org/10.3390/jlpea1010077
Zhang X, Leomant S, Lau KL, Bermak A. A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM. Journal of Low Power Electronics and Applications. 2011; 1(1):77-96. https://doi.org/10.3390/jlpea1010077
Chicago/Turabian StyleZhang, Xiaoxiao, Sylvain Leomant, Ka Lai Lau, and Amine Bermak. 2011. "A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM" Journal of Low Power Electronics and Applications 1, no. 1: 77-96. https://doi.org/10.3390/jlpea1010077