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Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations
Department of Electronics, Computer Science and Systems (DEIS), University of Calabria, Arcavacata di Rende-87036-Rende (CS), Italy
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Received: 25 November 2010; in revised form: 18 March 2011 / Accepted: 1 April 2011 / Published: 6 April 2011
Abstract: Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS) standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures) operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.
Keywords: intra-die process variations; yield-driven design; adder design
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Cite This Article
MDPI and ACS Style
Lanuzza, M.; Frustaci, F.; Perri, S.; Corsonello, P. Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations. J. Low Power Electron. Appl. 2011, 1, 97-108.
Lanuzza M, Frustaci F, Perri S, Corsonello P. Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations. Journal of Low Power Electronics and Applications. 2011; 1(1):97-108.
Lanuzza, Marco; Frustaci, Fabio; Perri, Stefania; Corsonello, Pasquale. 2011. "Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations." J. Low Power Electron. Appl. 1, no. 1: 97-108.