Table of Contents

Abstract: The proliferation of electronic devices has profoundly affected all aspects of modern life. Large populations of people worldwide are now acclimated to the use of modern electronic devices on a daily basis. Giant industrial corporations, commercial companies and small businesses all use a variety of computing, communications and electronic devices to increase their productivity, enhance market research and improve customer support and satisfaction. [...].

Abstract: Radiation induced transient faults like single event upsets (SEU) and multiple event upsets (MEU) in memories are well researched. As a result of the technology scaling, it is observed that the logic blocks are also vulnerable to malfunctioning when they are deployed in radiation prone environment. However, the current literature is lacking efforts to mitigate such issues in the digital logic circuits when exposed to natural radiation prone environment or when they are subjected to malicious attacks by an eavesdropper using highly energized particles. This may lead to catastrophe in critical applications such as widely used cryptographic hardware. In this paper, novel dynamic error correction architectures, based on the BCH codes, is proposed for correcting multiple errors which makes the circuits robust against radiation induced faults irrespective of the location of the errors. As a benchmark test case, the finite field multiplier circuit is considered as the functional block which can be the target for major attacks. The proposed scheme has the capability to handle stuck-at faults that are also a major cause of failure affecting the overall yield of a nano-CMOS integrated chip. The experimental results show that the proposed dynamic error detection and correction architecture results in 50% reduction in critical path delay by dynamically bypassing the error correction logic when no error is present. The area overhead for the larger multiplier is within 150% which is 33% lower than the TMR and comparable to 130% overhead of single error correcting Hamming and LDPC based techniques.

Abstract: We experimentally investigate the effects of Co-60 irradiation on the electrical properties of single-walled carbon nanotube and graphene field-effect transistors. We observe significant differences in the radiation response of devices depending on their irradiation environment, and confirm that, under controlled conditions, standard dielectric hardening approaches are applicable to carbon nanoelectronics devices.