Electronics 2012, 1(1), 3-22; doi:10.3390/electronics1010003

Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)

1 Oxford Brookes University, SOT, Wheatley Campus, OX33 1HX Oxford, UK 2 Department of Computer Science, University of Bristol, Merchant Venturers Building, Woodland Road, BS8 1UB Bristol, UK
* Author to whom correspondence should be addressed.
Received: 14 May 2012; in revised form: 29 May 2012 / Accepted: 11 June 2012 / Published: 26 June 2012
(This article belongs to the Special Issue Feature Papers)
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Abstract: Radiation induced transient faults like single event upsets (SEU) and multiple event upsets (MEU) in memories are well researched. As a result of the technology scaling, it is observed that the logic blocks are also vulnerable to malfunctioning when they are deployed in radiation prone environment. However, the current literature is lacking efforts to mitigate such issues in the digital logic circuits when exposed to natural radiation prone environment or when they are subjected to malicious attacks by an eavesdropper using highly energized particles. This may lead to catastrophe in critical applications such as widely used cryptographic hardware. In this paper, novel dynamic error correction architectures, based on the BCH codes, is proposed for correcting multiple errors which makes the circuits robust against radiation induced faults irrespective of the location of the errors. As a benchmark test case, the finite field multiplier circuit is considered as the functional block which can be the target for major attacks. The proposed scheme has the capability to handle stuck-at faults that are also a major cause of failure affecting the overall yield of a nano-CMOS integrated chip. The experimental results show that the proposed dynamic error detection and correction architecture results in 50% reduction in critical path delay by dynamically bypassing the error correction logic when no error is present. The area overhead for the larger multiplier is within 150% which is 33% lower than the TMR and comparable to 130% overhead of single error correcting Hamming and LDPC based techniques.
Keywords: Galois Field (GF); cryptography; Single Event Upset (SEU); Multiple Event Upset (MEU); Triple Modular Redundancy (TMR); error correction; fault tolerance

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MDPI and ACS Style

Poolakkaparambil, M.; Mathew, J.; Jabir, A. Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m). Electronics 2012, 1, 3-22.

AMA Style

Poolakkaparambil M, Mathew J, Jabir A. Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m). Electronics. 2012; 1(1):3-22.

Chicago/Turabian Style

Poolakkaparambil, Mahesh; Mathew, Jimson; Jabir, Abusaleh. 2012. "Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)." Electronics 1, no. 1: 3-22.

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