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J. Low Power Electron. Appl., Volume 7, Issue 4 (December 2017)

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Research

Open AccessArticle Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs
J. Low Power Electron. Appl. 2017, 7(4), 25; doi:10.3390/jlpea7040025
Received: 9 August 2017 / Revised: 27 September 2017 / Accepted: 27 September 2017 / Published: 3 October 2017
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Abstract
Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools
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Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet the power requirement. In this paper, we will evaluate, independently from the library file, the impact of redefining the max transition constraint (MTC) before the power optimization phase, and we will study the impact of over-constraining or under-constraining a design on power in order to find the best trade-off between design constraining and power optimization. Experimental results showed that power optimization depends on the applied MTC and that the MTC value corresponding to the best power reduction results is different from the default MTC. By using a new MTC definition method on several designs, we found that the power gain between the default methodology and the new one reaches 2.34%. Full article
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Open AccessArticle Inkjet Printed Fully-Passive Body-Worn Wireless Sensors for Smart and Connected Community (SCC)
J. Low Power Electron. Appl. 2017, 7(4), 26; doi:10.3390/jlpea7040026
Received: 30 September 2017 / Revised: 30 October 2017 / Accepted: 4 November 2017 / Published: 9 November 2017
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Abstract
Future Smart and Connected Communities (SCC) will utilize distributed sensors and embedded computing to seamlessly generate meaningful data that can assist individuals, communities, and society with interlocking physical, social, behavioral, economic, and infrastructural interaction. SCC will require newer technologies for seamless and unobtrusive
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Future Smart and Connected Communities (SCC) will utilize distributed sensors and embedded computing to seamlessly generate meaningful data that can assist individuals, communities, and society with interlocking physical, social, behavioral, economic, and infrastructural interaction. SCC will require newer technologies for seamless and unobtrusive sensing and computation in natural settings. This work presents a new technology for health monitoring with low-cost body-worn disposable fully passive electronic sensors, along with a scanner, smartphone app, and web-server for a complete smart sensor system framework. The novel wireless resistive analog passive (WRAP) sensors are printed using an inkjet printing (IJP) technique on paper with silver inks (Novacentrix Ag B40, sheet resistance of 21 mΩ/sq) and incorporate a few discrete surface mounted electronic components (overall thickness of <1 mm). These zero-power flexible sensors are powered through a wireless inductive link from a low-power scanner (500 mW during scanning burst of 100 ms) by amplitude modulation at the carrier signal of 13.56 MHz. While development of various WRAP sensors is ongoing, this paper describes development of a WRAP temperature sensor in detail as an illustration. The prototypes were functionally verified at various temperatures with energy consumption of as low as 50 mJ per scan. The data is analyzed with a smartphone app that computes severity (Events-of-Interest, or EoI) using a real-time algorithm. The severity can then be anonymously shared with a custom web-server, and visualized either in temporal or spatial domains. This research aims to reduce ER visits of patients by enabling self-monitoring, thereby improving community health for SSC. Full article
(This article belongs to the Special Issue Low-Power Electronic Circuits for Monolithic Smart Wireless Sensors)
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Open AccessArticle A Low-Power Active Self-Interference Cancellation Technique for SAW-Less FDD and Full-Duplex Receivers
J. Low Power Electron. Appl. 2017, 7(4), 27; doi:10.3390/jlpea7040027
Received: 29 September 2017 / Revised: 4 November 2017 / Accepted: 10 November 2017 / Published: 13 November 2017
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Abstract
An active self-interference (SI) cancellation technique for SAW-less receiver linearity improvement is proposed. The active canceler combines programmable gain and phase in a single stage and is co-designed with a highly-linear LNA, achieving low noise and low power. A cross-modulation mechanism of the
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An active self-interference (SI) cancellation technique for SAW-less receiver linearity improvement is proposed. The active canceler combines programmable gain and phase in a single stage and is co-designed with a highly-linear LNA, achieving low noise and low power. A cross-modulation mechanism of the SI canceler is identified and strongly suppressed thanks to the introduction of an internal resistive feedback, enabling high effective receiver IIP3. TX leakage of up to −4 dBm of power is suppressed by over 30 dB at the input of the LNA, with benefits for the entire receiver in terms of IIP3, IIP2, and reciprocal mixing. The design was done in a 40 nm CMOS technology. The system, including receiver and active SI canceler, consumes less than 25 mW of power. When the canceler is enabled, it has an NF of 3.9–4.6 dB between 1.7 and 2.4 GHz and an effective IIP3 greater than 35 dBm. Full article
(This article belongs to the Special Issue Low-Power Electronic Circuits for Monolithic Smart Wireless Sensors)
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Open AccessArticle Sleep Stage Classification by a Combination of Actigraphic and Heart Rate Signals
J. Low Power Electron. Appl. 2017, 7(4), 28; doi:10.3390/jlpea7040028
Received: 25 September 2017 / Revised: 9 November 2017 / Accepted: 9 November 2017 / Published: 13 November 2017
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Abstract
Although heart rate variability and actigraphic data have been used for sleep-wake or sleep stage classifications, there are few studies on the combined use of them. Recent wearable sensors, however, equip both pulse wave and actigraphic sensors. This paper presents results on the
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Although heart rate variability and actigraphic data have been used for sleep-wake or sleep stage classifications, there are few studies on the combined use of them. Recent wearable sensors, however, equip both pulse wave and actigraphic sensors. This paper presents results on the performance of sleep stage classification by a combination of heart rate and actigraphic signals. We studied 40,643 epochs (length 3 min) of polysomnographic data in 289 subjects. A combined model, consisting of autonomic functional indices from heart rate variability and body movement indices derived from actigraphic data, discriminated non-rapid-eye-movement (REM) sleep from waking/REM sleep with 76.9% sensitivity, 74.5% specificity, 75.8% accuracy, and a Cohen’s kappa of 0.514. The combination was also useful for discriminating between REM sleep and waking at 77.2% sensitivity, 72.3% specificity, 74.5% accuracy, and a kappa of 0.491. Full article
(This article belongs to the Special Issue Low-Power Electronic Circuits for Monolithic Smart Wireless Sensors)
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Open AccessArticle Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing
J. Low Power Electron. Appl. 2017, 7(4), 29; doi:10.3390/jlpea7040029
Received: 6 September 2017 / Revised: 26 October 2017 / Accepted: 13 November 2017 / Published: 17 November 2017
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Abstract
The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to
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The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively. Full article
(This article belongs to the Special Issue FPGA and Reconfigurable Computing)
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Open AccessArticle Modified Hermite Pulse-Based Wideband Communication for High-Speed Data Transfer in Wireless Sensor Applications
J. Low Power Electron. Appl. 2017, 7(4), 30; doi:10.3390/jlpea7040030
Received: 2 October 2017 / Revised: 20 November 2017 / Accepted: 28 November 2017 / Published: 1 December 2017
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Abstract
With technological advances in the field of communication, the need for reliable high-speed data transfer is increasing. The deployment of large number of wireless sensors for remote monitoring and control and streaming of high definition video, voice and image data, etc. are imposing
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With technological advances in the field of communication, the need for reliable high-speed data transfer is increasing. The deployment of large number of wireless sensors for remote monitoring and control and streaming of high definition video, voice and image data, etc. are imposing a challenge to the existing network bandwidth allocation for reliable communication. Two novel schemes for ultra-wide band (UWB) communication technology have been proposed in this paper with the key objective of intensifying the data rate by taking advantage of the orthogonal properties of the modified Hermite pulse (MHP). In the first scheme, a composite pulse is transmitted and in the second scheme, a sequence of multi-order orthogonal pulses is transmitted in the place of a single UWB pulse. The MHP pulses exhibit a mutually orthogonal property between different ordered pulses and due to this property, simultaneous transmission is achieved without collision in the UWB system, resulting in an increase in transmission capacity or improved bit error rate. The proposed schemes for enhanced data rate will offer high volume data monitoring, assessment, and control of wireless devices without overburdening the network bandwidth and pave the way for new platforms for future high-speed wireless sensor applications. Full article
(This article belongs to the Special Issue Low-Power Electronic Circuits for Monolithic Smart Wireless Sensors)
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Open AccessArticle Analysis of Sensitivity and Power Consumption of Chopping Techniques for Integrated Capacitive Sensor Interface Circuits
J. Low Power Electron. Appl. 2017, 7(4), 31; doi:10.3390/jlpea7040031
Received: 30 September 2017 / Revised: 1 December 2017 / Accepted: 3 December 2017 / Published: 7 December 2017
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Abstract
In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because
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In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because of its capability of reducing circuit noise at low frequencies. The capacitive sensitivity and power consumption of various chopping techniques including the dual chopper amplifier (DCA), single chopper amplifier (SCA) and two-stage single chopper amplifier (TCA) are extracted for different values of total gain and sensor capacitance. The minimum sensitivity for each technique will be extracted based on the gain and sensor capacitance. It will be shown that designation of the amplifier and distribution of gain in the TCA and DCA are important for sensitivity. A design procedure for chopper amplifiers that illustrates the steps required to achieve either the best or the desired sensitivity while minimizing power consumption will be presented. It will be shown that for a small sensor capacitance and large total gain, the DCA has the best sensitivity, while for a large sensor capacitance and a lower gain, the SCA is preferable. The TCA is the desired architecture for an average total gain and a large sensor capacitance. Moreover, when the power consumption is the key requirement and the maximum sensitivity is not the goal; the TCA works best due to its potential to decrease the power consumption. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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Open AccessArticle Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading
J. Low Power Electron. Appl. 2017, 7(4), 32; doi:10.3390/jlpea7040032
Received: 6 November 2017 / Revised: 5 December 2017 / Accepted: 12 December 2017 / Published: 14 December 2017
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Abstract
Much research focuses on many-core processors, which possess a vast number of cores. Their area, energy consumption, and performance have a tendency to be proportional to the number of cores. It is better to utilize in-order (IO) execution for better area/energy efficiency. However,
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Much research focuses on many-core processors, which possess a vast number of cores. Their area, energy consumption, and performance have a tendency to be proportional to the number of cores. It is better to utilize in-order (IO) execution for better area/energy efficiency. However, expanding two-way IO to three-way IO offers very little improvement, since data dependency limits the effectiveness. In addition, if the core is changed from IO to out-of-order (OoO) execution to improve Instruction Per Cycle(IPC), area and energy consumption increases significantly. The combination of IO execution and Arithmetic Logic Unit(ALU) cascading is an effective solution to alleviate this problem. However, ALU cascading is implemented by complex bypass circuits because it requires a connection between all outputs and all inputs of all ALUs. The hardware complexity of the bypass circuits increases area, energy consumption, and delay. In this study, we proposed a mechanism that limits the number of the forwarding paths and allocates instructions to ALUs in accordance with the limited paths. This mechanism scales down bypass circuits to reduce the hardware complexity. Our evaluation results show that our proposed mechanism can reduce the area by 38.7%, the energy by 41.1%, and the delay by 23.2% with very little IPC loss on average, as compared with the conventional mechanism. Full article
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Open AccessArticle A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications
J. Low Power Electron. Appl. 2017, 7(4), 33; doi:10.3390/jlpea7040033
Received: 20 September 2017 / Revised: 8 December 2017 / Accepted: 12 December 2017 / Published: 18 December 2017
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Abstract
Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In
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Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In this paper, a low-power CMOS full-bridge rectifier is presented as a potential solution for an efficient energy harvesting system for piezoelectric transducers. The energy harvesting circuit consists of two n-channel MOSFETs (NMOS) and two p-channel MOSFETs (PMOS) devices implementing a full-bridge rectifier coupled with a switch control circuit based on a PMOS device driven by a comparator. With a load of 45 kΩ, the output rectifier voltage and the input piezoelectric transducer voltage are 694 mV and 703 mV, respectably, while the VOUT versus VIN conversion ratio is 98.7% with a PCE of 52.2%. The energy harvesting circuit has been designed using 130 nm standard CMOS process. Full article
(This article belongs to the Special Issue Low-Power Electronic Circuits for Monolithic Smart Wireless Sensors)
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