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J. Low Power Electron. Appl. 2016, 6(3), 16; doi:10.3390/jlpea6030016

Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions

School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
This paper is an extended version of our paper publishered in 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015).
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Academic Editors: Osnat Keren, Ilia Polian and Sanu Mathew
Received: 11 July 2016 / Revised: 18 August 2016 / Accepted: 18 August 2016 / Published: 24 August 2016
View Full-Text   |   Download PDF [1635 KB, uploaded 24 August 2016]   |  

Abstract

Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model. View Full-Text
Keywords: physical unclonable function (PUF); hardware security; Static Random Access Memory (SRAM); process variation; memory failures physical unclonable function (PUF); hardware security; Static Random Access Memory (SRAM); process variation; memory failures
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Chang, C.-H.; Liu, C.Q.; Zhang, L.; Kong, Z.H. Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions. J. Low Power Electron. Appl. 2016, 6, 16.

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