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J. Low Power Electron. Appl. 2016, 6(3), 15; doi:10.3390/jlpea6030015

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology

1
and
2,*
1
Computer Engineering Program, California State University, Fullerton, CA 92831, USA
2
Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32817, USA
*
Author to whom correspondence should be addressed.
Academic Editors: Ka Lok Man, M. L. Dennis Wong and Chao Lu
Received: 17 May 2016 / Revised: 28 July 2016 / Accepted: 29 July 2016 / Published: 12 August 2016
(This article belongs to the Special Issue Recent Advances in Emerging Low Power Circuits and Systems)
View Full-Text   |   Download PDF [3333 KB, uploaded 20 September 2016]   |  

Abstract

This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits. View Full-Text
Keywords: emerging devices; FPGA; stochastic computing emerging devices; FPGA; stochastic computing
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Bai, Y.; Lin, M. Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology. J. Low Power Electron. Appl. 2016, 6, 15.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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