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J. Low Power Electron. Appl. 2015, 5(3), 183-215; doi:10.3390/jlpea5030183

Delay Insensitive Ternary CMOS Logic for Secure Hardware

1
University of Arkansas, Fayetteville, AR 72701, USA
2
Electrical and Computer Engineering at North Dakota State University, Fargo, ND 58108, USA
3
Computer Science & Computer Engineering at University of Arkansas, Fayetteville, AR 72701, USA
*
Author to whom correspondence should be addressed.
Academic Editor: Alexander Fish
Received: 29 May 2015 / Accepted: 31 August 2015 / Published: 11 September 2015
(This article belongs to the Special Issue Low-Power Asynchronous Circuits)
View Full-Text   |   Download PDF [2872 KB, uploaded 11 September 2015]   |  

Abstract

As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU. View Full-Text
Keywords: Asynchronous Logic; Delay Insensitive Logic; Ternary Logic; Digital Design; NCL; Secure Circuits Asynchronous Logic; Delay Insensitive Logic; Ternary Logic; Digital Design; NCL; Secure Circuits
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Nair, R.S.P.; Smith, S.C.; Di, J. Delay Insensitive Ternary CMOS Logic for Secure Hardware. J. Low Power Electron. Appl. 2015, 5, 183-215.

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