Next Article in Journal
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits
Next Article in Special Issue
Delay Insensitive Ternary CMOS Logic for Secure Hardware
Previous Article in Journal
Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View
Article Menu

Export Article

Open AccessArticle
J. Low Power Electron. Appl. 2015, 5(2), 81-100; doi:10.3390/jlpea5020081

Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology

1
Advanced Micro Devices, Inc., Sunnyvale, CA 94089, USA
2
Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA
3
Department of Electrical & Computer Engineering, North Dakota State University, Fargo, ND 58108, USA
4
Department of Computer Science & Computer Engineering, University of Arkansas, Fayetteville, AR 72701, USA
*
Author to whom correspondence should be addressed.
Academic Editor: Alexander Fish
Received: 15 December 2014 / Accepted: 6 May 2015 / Published: 18 May 2015
(This article belongs to the Special Issue Low-Power Asynchronous Circuits)

Abstract

This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster. View Full-Text
Keywords: NULL convention logic (NCL); multi-threshold CMOS (MTCMOS); sleep convention logic (SCL) NULL convention logic (NCL); multi-threshold CMOS (MTCMOS); sleep convention logic (SCL)
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

Scifeed alert for new publications

Never miss any articles matching your research from any publisher
  • Get alerts for new papers matching your research
  • Find out the new papers from selected authors
  • Updated daily for 49'000+ journals and 6000+ publishers
  • Define your Scifeed now

SciFeed Share & Cite This Article

MDPI and ACS Style

Zhou, L.; Parameswaran, R.; Parsan, F.A.; Smith, S.C.; Di, J. Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology. J. Low Power Electron. Appl. 2015, 5, 81-100.

Show more citation formats Show less citations formats

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top