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J. Low Power Electron. Appl. 2015, 5(4), 216-233; doi:10.3390/jlpea5040216

Radiation Hardened NULL Convention Logic Asynchronous Circuit Design

1,* , 2,†
and
3,†
1
NVIDIA Corporation, Santa Clara, CA 95050, USA
2
Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58108, USA
3
Department of Computer Science & Computer Engineering, University of Arkansas, Fayetteville, AR 72701, USA
These authors contributed equally to this work.
*
Author to whom correspondence should be addressed.
Academic Editor: Alexander Fish
Received: 19 July 2015 / Revised: 29 August 2015 / Accepted: 13 October 2015 / Published: 20 October 2015
(This article belongs to the Special Issue Low-Power Asynchronous Circuits)
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Abstract

This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead. View Full-Text
Keywords: NULL Convention Logic (NCL); single event upset (SEU); single event latchup (SEL); radiation hardening by design NULL Convention Logic (NCL); single event upset (SEU); single event latchup (SEL); radiation hardening by design
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Zhou, L.; Smith, S.C.; Di, J. Radiation Hardened NULL Convention Logic Asynchronous Circuit Design. J. Low Power Electron. Appl. 2015, 5, 216-233.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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