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Hardware Implementation of an Automatic Rendering Tone Mapping Algorithm for a Wide Dynamic Range Display
Integrated Sensors, Intelligent Systems (ISIS) Laboratory, Electrical and Computer Engineering Department, University of Calgary, Calgary, AB T2N 1N4, Canada
VLSI Systems Center, Ben-Gurion University of the Negev, POB 653, Beer-Sheva 84105, Israel
* Author to whom correspondence should be addressed.
Received: 24 June 2013; in revised form: 12 August 2013 / Accepted: 9 September 2013 / Published: 29 October 2013
Abstract: Tone mapping algorithms are used to adapt captured wide dynamic range (WDR) scenes to the limited dynamic range of available display devices. Although there are several tone mapping algorithms available, most of them require manual tuning of their rendering parameters. In addition, the high complexities of some of these algorithms make it difficult to implement efficient real-time hardware systems. In this work, a real-time hardware implementation of an exponent-based tone mapping algorithm is presented. The algorithm performs a mixture of both global and local compression on colored WDR images. An automatic parameter selector has been proposed for the tone mapping algorithm in order to achieve good tone-mapped images without manual reconfiguration of the algorithm for each WDR image. Both algorithms are described in Verilog and synthesized for a field programmable gate array (FPGA). The hardware architecture employs a combination of parallelism and system pipelining, so as to achieve a high performance in power consumption, hardware resources usage and processing speed. Results show that the hardware architecture produces images of good visual quality that can be compared to software-based tone mapping algorithms. High peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) scores were obtained when the results were compared with output images obtained from software simulations using MATLAB.
Keywords: tone mapping; wide dynamic range (WDR); high dynamic range (HDR); CMOS image sensors; hardware implementation; field programmable gate array (FPGA)
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MDPI and ACS Style
Ofili, C.; Glozman, S.; Yadid-Pecht, O. Hardware Implementation of an Automatic Rendering Tone Mapping Algorithm for a Wide Dynamic Range Display. J. Low Power Electron. Appl. 2013, 3, 337-367.
Ofili C, Glozman S, Yadid-Pecht O. Hardware Implementation of an Automatic Rendering Tone Mapping Algorithm for a Wide Dynamic Range Display. Journal of Low Power Electronics and Applications. 2013; 3(4):337-367.
Ofili, Chika; Glozman, Stanislav; Yadid-Pecht, Orly. 2013. "Hardware Implementation of an Automatic Rendering Tone Mapping Algorithm for a Wide Dynamic Range Display." J. Low Power Electron. Appl. 3, no. 4: 337-367.