Open AccessThis article is
- freely available
Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS
VTT Technical Research Centre of Finland, FI-02044 VTT, Finland
Department of Micro- and Nanosciences, Aalto University, FI-00076 Aalto, Finland
* Author to whom correspondence should be addressed.
Received: 2 March 2012; in revised form: 29 May 2012 / Accepted: 30 May 2012 / Published: 6 June 2012
Abstract: This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV.
Keywords: subthreshold; ultra-low-power; timing-error detection; subthreshold source-coupled logic; SCL; weak inversion; dynamic supply voltage; dynamic voltage scaling
Citations to this Article
Cite This Article
MDPI and ACS Style
Mäkipää, J.; Turnquist, M.J.; Laulainen, E.; Koskinen, L. Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS. J. Low Power Electron. Appl. 2012, 2, 180-196.
Mäkipää J, Turnquist MJ, Laulainen E, Koskinen L. Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS. Journal of Low Power Electronics and Applications. 2012; 2(2):180-196.
Mäkipää, Jani; Turnquist, Matthew J.; Laulainen, Erkka; Koskinen, Lauri. 2012. "Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS." J. Low Power Electron. Appl. 2, no. 2: 180-196.