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A Minimum Leakage Quasi-Static RAM Bitcell
Low Power Circuits and Systems Lab (LPC&S), The VLSI Systems Center, Ben-Gurion University of the Negev, P.O. Box 653, Be’er Sheva, 84105, Israel
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Received: 25 November 2010; in revised form: 2 May 2011 / Accepted: 3 May 2011 / Published: 16 May 2011
Abstract: As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.
Keywords: CMOS memory integrated circuits; SRAM; leakage suppression; ultra low power; dynamic noise margin
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Cite This Article
MDPI and ACS Style
Teman, A.; Pergament, L.; Cohen, O.; Fish, A. A Minimum Leakage Quasi-Static RAM Bitcell. J. Low Power Electron. Appl. 2011, 1, 204-218.
Teman A, Pergament L, Cohen O, Fish A. A Minimum Leakage Quasi-Static RAM Bitcell. Journal of Low Power Electronics and Applications. 2011; 1(1):204-218.
Teman, Adam; Pergament, Lidor; Cohen, Omer; Fish, Alexander. 2011. "A Minimum Leakage Quasi-Static RAM Bitcell." J. Low Power Electron. Appl. 1, no. 1: 204-218.