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This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/).

Low-power circuit design techniques have enabled the possibility of integrating signal processing and feature extraction algorithms on-board implantable medical devices, eliminating the need for wireless transfer of data outside the patient. Feature extraction algorithms also serve as valuable tools for modern-day artificial prostheses, made possible by implantable brain-computer-interface systems. This paper intends to review the challenges in designing feature extraction blocks for implantable devices, with specific focus on developing efficacious but computationally efficient algorithms to detect seizures. Common seizure detection features used to construct algorithms are evaluated and algorithmic, mathematical as well as circuit-level design techniques are suggested to effectively translate the algorithms into hardware implementations on low-power platforms.

Epilepsy affects over 1% of the world's population with over 10 million sufferers in the United States alone, making it the second most common neurological disorder after stroke [

Effective seizure prediction or detection algorithms present the key to realize such “closed-loop” epilepsy treatment devices that deliver electrical stimulus upon detection of seizure activity. Algorithms to detect onset of electrographic seizures have been actively researched for the past two decades with mixed success. Even the few real-time detection algorithms reported are limited to non-portable bedside setups using one or more computers interfacing to recording electrodes implanted in the patient. Peters

In the context of closed-loop epilepsy therapeutic devices, signal processing allows for integrating responsive seizure detection or prediction algorithms to analyze the recorded neural data and apply interventional therapy in a temporally specific manner. While there have been a number of different approaches proposed to both predict and detect seizures, barely a handful of these algorithms are employed into portable computing devices-implantable or hand-held. The computational limitations imposed by a battery powered platform limit most of the proposed real-time algorithms to purely theory or non-portable bedside applications for in-hospital monitoring. One proposed solution to this limitation is to use wireless schemes to transmit in real-time the data recorded from the patient on to an external device running the algorithms. Wireless transmitters often occupy a majority of area in the power consumption pie-chart of implantable medical devices- sometimes consuming more power than the rest of the system [

This article intends to highlight the challenges in realizing efficient feature extraction algorithms at a low computational cost, in order to retain implant feasibility. We review a set of techniques to translate mathematical models into computationally efficient hardware implementations so as to avoid the use of continuous transmission of data outside the implant. The next section overviews the major building blocks that go into a closed-loop epilepsy prosthesis. This is followed by an elaboration on digital feature extraction algorithms with specific reference to seizure detection. Low-power design techniques are then discussed with different levels of abstraction from mathematical to algorithmic, to improve the efficacy of the discussed seizure detection algorithms. It is our intention to involve the low-power circuit design community into developing novel solutions to this growing application space of medical implants, by using epilepsy treatment devices as an example.

In order to develop closed-loop automated epilepsy treatment devices employing electrical stimulation, it is crucial to implement computationally efficient and highly specific seizure detection algorithms that trigger interventional therapy when necessary. The detection efficacy of the algorithm employed controls the overall power budget of the implanted system (by controlling the number of times a large electrical stimulus is applied) besides deciding the utility of responsive therapy. Typically, such systems consist of an analog low-noise front end which includes a neural recording amplifier with the necessary filtering and at least 40dB of gain [

Historically, seizure detection algorithms have mostly been targeted at bedside patient monitoring and offline data sorting applications to easily identify seizure events from months of patient data [

Recently Verma

The most straightforward analog signal encoding schemes use a simple one-bit comparator to threshold (spike detect) data, reducing the neural signal to digital spike or threshold-crossings [

Another analog feature extraction scheme aims to track the energy present in local field potential signals in a narrow range of frequencies (e.g., 20–40 Hz), with the idea that a slower ADC could then be used to digitize this specific band of information. The proposed implementation uses a leaky integrator with a band-pass filter and squaring circuit to estimate the LFP energy from raw neural data [

Digital feature extraction algorithms assume the presence of an on-board ADC that provides sufficient resolution to capture the required information from raw data. Since most of the neural recording applications do not require high bandwidth (less than 10 KS/s per channel), standard Successive-Approximation ADCs remain a popular choice for this category [

Digital schemes are the most widely applied and generic signal processing modules applied in medical implants. Digital signal processing comes at low hardware costs and can integrate maximal functionality per unit silicon area occupied especially with scaled technologies. Given that medical implants normally do not demand high clock-speed performance, the digital designs also allow for severe voltage scaling operating in near to sub-threshold regions of operation [

In this section, we review common features used to identify electrographic seizures from raw neural data. Seizure detection features usually rely on characteristic attributes in a seizure that are identified by mathematical differences from normal or “baseline” activity. These features could either be time or frequency based.

Frequency based operators normally involve computationally intense feature extraction involving evaluation of FFTs, which reduce their viability as one of multiple features on board an implantable device. However, custom implementations of digital/analog circuits to extract an estimate of dominant frequency may be applied to approximate the mathematical feature, provided the detection efficacy validates this trade-off, as shown by our group in the past [

This subsection intends to review some of the basic terminology essential to understanding the issues in evaluating seizure detection algorithms designed for implantable devices. Typically, the detection efficacy of an algorithm or feature is defined by its ability to (i) accurately identify the onset of a seizure and (ii) reject any “seizure-like” short artifacts that could lead to unnecessary stimulation. The former is quantified by a measure of its sensitivity and the latter by specificity. Detection delay is defined as the amount of time after electrographic seizure onset that the algorithm identifies it. There exists uncertainty surrounding the definition of “onset”, and the only current gold-standard is visual inspection by electroencephalography experts trained in reading epileptic patterns.

Another distinction that is important to evaluate the efficacy of an algorithm is its performance in a real-time, look-ahead or prospective study. In other words, using a training set that is different than a testing set would allow for an unbiased evaluation of the algorithm's detection capabilities. Most detection algorithms use some variant of moving windows to average data points to extract features. The size of the window used has a direct implication on detection delay, trading off with false positives and negatives. Recently, Mormann et al. reviewed a comprehensive list of seizure prediction algorithms published in the literature and concluded that not one algorithm showed a performance better than statistical chance when subjected to a look-ahead, unbiased evaluation [

We compared a set of time and frequency based operators to quantify their ability as markers of electrographic seizure activity. The analysis performed was “retrospective”; without separate training and testing sets. The efficacy numbers obtained using such an analysis reflect the theoretical best case performance of these features and give the designer an idea of what features to select to construct an optimal seizure detection algorithm.

For purposes of unbiased comparison, an equal window size of ∼1 s (1526 samples from data sampled at 1.5 KHz) was used to evaluate the features. The animal data was separated out into baseline and seizures (as identified by epileptologists at the IU School of Medicine) and the test intended to quantify the ability of the feature under study to distinguish these two states. It is to be noted that the seizures used were all electrographic-without consideration for whether there were clinical symptoms associated. The difference in mean values during baseline and seizure were calculated for each of the features under study, and the significance of this difference estimated using the t-test. The statistical power of the test was also reported to give the reader an idea of the significance of the difference in means, given the sample size and variance in each data. To help visualize the demarcation between seizure and baseline data for each feature, we fitted the values into a normal distribution, and calculated the area of overlap between the baseline and seizure fits. A smaller overlap indicates a better demarcation between the two states-indicating the ability of the feature to better separate these two states and vice-versa.

The results from the comparison (

The features with higher detection efficacies also came with a higher associated hardware cost.

For example, an algorithm requiring using spectral analysis (any of the frequency based operators compared in

In the

On the other hand, implementing a discrete wavelet transform operator (DWT) allows for a much finer time and frequency resolution at a lower hardware cost than traditional FFT or STFT operations for large windows of data. Recently, we reported a DWT-based detection algorithm implemented on silicon with multiplier-less filters, that demonstrates for optimal detection performance at a low hardware cost [

This section reviews a set of design techniques in different levels of hierarchy that could be applied to make the hardware implementations of the digital features more power efficient. In the past, we have proposed specific algorithmic approximations to optimize combinations of a set of compared features, demonstrating its benefit over un-optimized or blind combination [

The data presented in

Floating point division is one of the more computationally intense operators, and is commonly employed in realizing mathematical functions. While a floating point division operation takes 2911 clock cycles on the MC68HC11 processor(used by Medtronic for a number of implantable neurostimulators), a fixed point division operation only requires 41 clock cycles. Employing various division algorithms to reduce the number of clock cycles required to complete the operation has been widely researched in the past. Floating point division, for example, is commonly approximated using fixed point division with a number that has been “scaled” to account for precision retention. With specific reference to the implementation of seizure detection algorithms, most detection features use a form of averaging (moving window averaging) to ensure that short-term non-linearities in the raw signal do not affect the metric. Windowing involves accumulation and division by the window size. If the divisor (window size) can be approximated to a power of 2 (say 2^{m}), the quotient can be computed by simply shifting the dividend towards the least significant bit by ‘m’ bits. If the number of samples in the window used to average each feature is large, such an approximation of the divisor would not significantly affect the performance of the algorithm. Alternately, the window size may be left unaltered and divisor could be approximated to the nearest power of two to get similar results. This design choice should be made based on the magnitude of the approximation error resulting from both these options.

Division approximations that can be implemented using simple microcontrollers or even custom digital logic would be highly preferred for applications such as multi-channel neural data acquisition systems, that deal with relatively higher speed clock operations imposed by high sampling rate and number of channels. Drew presents a division approximation along with its hardware implementation in the referenced disclosure which involves ratio estimation to determine the ratio of a numerator to a denominator as a result of a function of 2 raised to the power of the difference between the most significant set bit position (MSSB) of denominator to numerator [

This is easily implemented in hardware using a single accumulator or binary counter that may be incremented up or down to obtain the desired ratio per

A number of detection features employ overlapped windows to accurately capture the effect of every sample on the mathematical feature. This is especially more important for features working on data sampled at lower frequencies. _{i}^{th}

A “quasi-averaging” technique recently reported approximates this calculation by assuming that “the average of a window is a true representation of all the elements contained in it”, re-writing this equation as

Frequency based features often involve implementing FIR or IIR filters in hardware. From a hardware perspective, ultra-low power FIR filters operating using sub-threshold circuits have been proposed for other medical applications such as hearing aids in the past [

This approximation made to the coefficients shows negligible degradation in the filter response for applications such as epileptic seizure detection, as shown by the authors who implemented a discrete-wavelet-transform (DWT) based seizure detection algorithm using the above described CSHM filter [

From the results in

Approximations made to the algorithm or feature under study is another level of design abstraction that can reduce hardware costs of digital features. While this kind of design modification is very application specific and hard to generalize, there have been published reports in the past employing such techniques to minimize hardware power consumption. Reviewing the results of the two-dimensional comparison study presented earlier and in [^{2} and another to evaluate ^{2}. In the ^{th}

The _{k}_{−1}” instead of the present window “

Another example of an algorithmic approximation to facilitate simple hardware implementation aims to estimate the dominant frequency of neural data by calculating the time between spike thresholds, or “events” [

The approximation is subject to the correct amplitude threshold being set to ensure the spikes are not missed by the comparator- reducing its robustness and mathematical accuracy with any variations in this threshold with time. However, with adaptive spike thresholding techniques that have been proposed in the past, it is possible to constantly adapt the threshold with changing DC levels of raw neural data [

Implantable medical devices usually do not have high impositions on throughput (typically operating under 1-MHz), allowing for aggressive supply voltage scaling (V_{DD}_{DD}_{DD}

Operation in the sub-threshold region results in increased susceptibility of circuits to process variations, making it imperative to employ circuit techniques to counter the adverse effects of process variations on circuit functionality, power and performance. Moreover, due to the low frequency operation of the system, leakage energy becomes dominant over dynamic energy. Leakage reduction techniques need to be used to achieve overall reduction in the energy consumption of the system. In the subsequent sub-sections, we review such design techniques in detail. A discussion on the optimal V_{DD}

_{DD}_{DD}_{DD}_{DD}_{DD}_{DD}_{DD}

In an example of a 5000 inverter chain implemented in TSMC65 nm, we discuss the simulation results showing leakage and dynamic power and energies at different V_{DD}_{DD}_{DD}_{DDL}_{opt}

The _{DD}_{DD}_{DD}_{DD}_{DD}

Operation of circuits in the sub-threshold region leads to increased sensitivity to process variations [_{M}_{M}_{DD}_{M}_{M}_{ref}_{1} and V_{ref}_{2}, V_{ref}_{1} being smaller than V_{ref}_{2}. If V_{M}_{ref}_{1}, implying weaker PMOS, forward bias is applied to the body of PMOS, increasing its strength. Similarly, if V_{M}_{ref}_{2}, implying stronger PMOS, reverse body bias is applied to PMOS. If V_{ref}_{1} < V_{M}_{ref}_{2}, no body bias is applied. Measurement results on a chip fabricated in 130 nm CMOS technology show a 17% reduction in the spread of V_{M}

In this sub-section, we briefly review some of the block level circuit designs proposed to reduce either active or leakage energy consumption. While some of the techniques discussed also find broader application from a system-level design abstraction, others help in realizing low-power computational blocks optimized for lower throughput application platforms such as medical implants.

Transistors in series have been shown to expend lower leakage power [_{X}

One of the most common approaches to decrease the dynamic component of total power consumption is to disable the clock driving inactive circuit blocks. This approach is used in both low power [

A fully programmable seizure-detection subsystem that incorporates four different hardware-optimized detection features from the study results reported by Raghunathan

The “Phoenix” processor proposed by researchers at the University of Michigan widely employs power gating to reduce leakage or “standby” power consumption [_{t}_{t}

The design of low-power seizure detection algorithms would facilitate integration of responsive feedback therapy to suppress epileptic seizures in an implantable device. Given the number of mathematical models proposed to both predict and detect seizures in human and animal trials, translational research that adapts these algorithms into designing a clinical device to treat epilepsy would be the logical next step to realize clinical impact. There are several components that go into developing a long-term neural implant that can reliably sense, detect and stimulate a specific part of the brain in order to suppress electrographic seizures. One of the main goals of this paper is to perform a review of circuit and architecture based techniques to implement feature extraction algorithms on board an implantable device- specifically for the treatment of epilepsy by neurostimulation. The techniques reviewed in this paper and results presented allow for translation of the many mathematical models presented over the past few decades from computer or offline implementations to a practical, portable device that can be of use to a patient. Examples from literature have been analyzed, where applicable, and related back to its utility in low-performance, low-power application platforms such as the one under study.

In this review, we set the stage by reviewing the parts of a closed-loop epilepsy treatment device, and drive the need for on-board signal processing capabilities to increase the power efficiency of these implants. Broadly, such techniques are applicable for most implantable medical device designs that are battery limited. Specific feature extraction algorithms to detect seizures are then discussed, with an emphasis on key terminology and examples from literature. Finally, Section 4 intends to provide the designers with a set of design techniques from various level of abstraction to optimize the implementation of digital feature extraction algorithms on a low-power implant.

Feature extraction, or signal processing represents a key aspect to realizing fully-implantable, single chip solutions to treat chronic disorders such as epilepsy. On-board signal processing would eliminate the need to transmit any data, wired or wireless, outside the body and therefore reduce a significant part of the power consumption of the device. We review specific examples applied to seizure detection algorithms and propose a set of techniques that could enable low-power algorithm design for a broad range of implantable medical devices. A set of both time and frequency based seizure detection features, commonly reported in the literature are evaluated for their feasibility in implantable applications. Approximations proposed in mathematical, algorithmic and circuit levels of abstraction allow for optimally trading off detection efficacy with low-power hardware feasibility. With rapid developments in micro-electrode fabrication technology as well as low-power design methodologies, realizing a closed-loop implant that would provide a solution for a large part of the non-respondent epileptic population is closer to a reality. Interdisciplinary collaboration would encourage rapid development of the next generation of neural implants that could treat epilepsy and a number of other chronic medical disorders that plague our society today.

Illustration showing the blocks that constitute a closed-loop epilepsy prosthesis to detect and suppress seizures via electrical stimulation.

Conceptual figure illustrating the different types of feature extraction schemes typically reported in literature to build implantable neural prostheses.

(Left) Adaptive spike detection circuitry proposed by Harrison (2003) and (Right) Application specific neuron-inspired ADC proposed by Yang

(Left) System architecture of a digital seizure detection algorithm developed by our group, adapted from Raghunathan

Snapshot of algorithm output (in blue) on animal data (in black) with false positive (FP), true negative (TN) and detection delay marked out for the defined electrographic seizure.

Normal fit of baseline and seizure data using example features “coastline”, “variance” and “autocorrelation” to calculate area of overlap.

Two dimensional detection algorithm design space contrasting both algorithm and hardware efficacy on the same plot, adapted from Raghunathan

Classification of design optimizations for low-power hardware realization at different levels of abstraction discussed in this review.

Block diagram of hardware implementation of a multiplier-less FIR filter proposed by Karakonstantis

Two-dimensional design space proposed by Raghunathan

Event-based seizure detection algorithm hardware proposed by our group that extracts dominant frequency by digitizing the “inter-event-interval”, reproduced from [

Figure adapted from [

Figure reproduced from [

Figure adapted from [

Timing diagram illustrating power-gating benefits in terms of energy per operation for a sample circuit (5000 inverter chain).

The effect of adaptive beta ration modulation (ABRM) shown with a schematic and its resulting improvement in the distribution of logic threshold voltage, adapted from [

Schematic illustrating the use of leakage control “stack” transistors, adapted from [

Event-based seizure detection algorithm reported by Raghunathan

Multi-algorithm seizure detection processor under development by our group based on results obtained from [

Classification of example seizure detection features.

| |
---|---|

Energy | Edge frequency |

Coastline/Line length | Spectral power |

Hjorth variance | Dominant frequency |

RMS amplitude | Dominant bandwidth |

Non-linear energy | Wavelet energy |

Autocorrelation | |

Rectified variance energy |

Results of retrospective analysis of seizure detection features.

Feature | Mean |
Mean |
Average |
t Value | Pr(| |
Area of |
Power |
---|---|---|---|---|---|---|---|

Energy | 380.64 | 4990.47 | 4727.04 | 2.44 | 0.071 | 0.43 | 0.698 |

Coastline | 2741.29 | 7192.26 | 4450.98 | 8.32 | 0.0011 | 0.16 | 0.999 |

Hjorth | 378.48 | 3702.97 | 3324.48 | 4.87 | 0.0082 | 0.09 | 0.996 |

RMS | 16.43 | 60.12 | 43.69 | 4.61 | 0.01 | 0.08 | 0.994 |

Autocorrelation | 1726.9 | 3934.8 | 2207.9 | 4.32 | 0.0125 | 0.31 | 0.9657 |

Abs. Variance | 1.44 × 10^{5} |
2.40 × 10^{6} |
2.25 × 10^{6} |
2.56 | 0.0626 | 0.65 | 0.7355 |

SEFa | 36.92 | 36.94 | 0.01 | 0.05 | 0.9566 | 0.79 | 0.0502 |

SEFb | 72.23 | 75.09 | 2.86 | 0.8 | 0.4705 | 0.58 | 0.0579 |

Sp Powera | 589.81 | 4486.4 | 3896.59 | 3.18 | 0.0335 | 0.16 | 0.8133 |

Sp Powerb | 1744.4 | 8509.6 | 6765.2 | 2.36 | 0.0782 | 0.15 | 0.4575 |

Dom Peak | 30.27 | 29.72 | −0.56 | 0.46 | 0.6709 | 0.87 | 0.0664 |

Peak BW | 9.79 | 9.56 | −0.24 | 0.36 | 0.738 | 0.87 | 0.0571 |

Normalized hardware cost of common mathematical operations used to construct algorithms.

Barrel shift Addition | 10-bit | 1× |

(a) RPL | 1.43 × | |

(b) CLA | 1.05× | |

Subtraction | (a) RPL | 1.53× |

(b) CLA | 1.15× | |

Multiplication | (a) CSA | 17.53× |

(b) Wallace-tree | 21.35× | |

Division | (a) RPL | 9.98 × |

(b) CLA | 9.33 × | |

Square root | (a) RPL | 15.06× |

(b) CLA | 16.54× |

Co-efficient approximation using “Shift and Add”.

25 (0011) | |

27 (0001) |

Table with simulated results to quantify leakage and dynamic energy of a test circuit with and without power-gating in a biomedical application scenario. (Fixed input frequency).

| ||||||
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1.1-V | 0.53-pJ | 4.75-pJ | 5.28-pJ | 14000-pJ | 4.75-pJ | 14005-pJ |

0.6-V | 0.27-pJ | 0.88-pJ | 1.15-pJ | 2610-pJ | 0.88-pJ | 2611-pJ |

0.1-V | 10.9-pJ | 0.81-pJ | 11.31-pJ | 160-pJ | 0.81-pJ | 161-pJ |