Recently Verma et al., demonstrated that employing a custom feature extraction processor to transmit relevant markers of epileptic seizures would reduce the amount of time a wireless transmitter would need to be powered and estimated a 93% improvement in power when feature extraction was applied [18]. Similar results have been reported by other literature on this subject [20]. The RF components of the device consume the most power when operated—sometimes an order of magnitude more than the rest of the system. With the need to transmit through longer distances and through skin and tissue, RF transmission schemes are required to be more robust while still remaining low-power. For epilepsy prostheses, the possibility of integrating seizure detection or prediction algorithms on board the implant eliminates the need to transmit any data outside of the implant besides programming and housekeeping information during startup. There have been two broad methods to extract meaningful information from neural data- analog and digital. Traditionally, analog schemes are thought of to be more power hungry, although there have been low-power implementations of analog feature extraction circuits proposed lately [27,28]. Analog circuit techniques do not require an ADC to accurately digitize neural signals- a challenging design given the dynamic range of neural signals. Figure 2 shows a block diagram of the possible feature extraction schemes that are normally applied to implantable medical devices.

The most straightforward analog signal encoding schemes use a simple one-bit comparator to threshold (spike detect) data, reducing the neural signal to digital spike or threshold-crossings [27,29]. The value of the chosen amplitude threshold is critical in deciding the efficacy of this technique. This simple digitization scheme is justified by the fact that most neuroprosthetic applications only require timing information from spikes (action potentials) accurate to about 1-ms [20]. Harrison et al., proposed an adaptive neural spike detection circuit to reduce the data transmission rate of a 100-electrode neural recording system from 1.5 Mb/s to 100 kb/s by only transmitting a 1-bit threshold crossing per channel [20]. While the 100 channel system used a standard comparator with programmable threshold, the authors also proposed an adaptive automatic threshold setting comparator design [27]. The adaptive scheme works on the assumption that the background noise from neural recordings is accurately represented by a Gaussian distribution and can be described by its rms value, equivalent to its standard deviation. Figure 3 shows the block diagram proposed by Harrison et al., which uses two comparators and a servo feedback loop that ensures that the second comparator performs spike detection using a specific multiple of the background noise rms value.

Another analog feature extraction scheme aims to track the energy present in local field potential signals in a narrow range of frequencies (e.g., 20–40 Hz), with the idea that a slower ADC could then be used to digitize this specific band of information. The proposed implementation uses a leaky integrator with a band-pass filter and squaring circuit to estimate the LFP energy from raw neural data [28]. An example contrasting digital and analog implementations of a filter for a seizure detection algorithm concludes that the analog implementation was able to perform with comparable accuracy and lower power consumption than using FPGA based digital implementations [33]. In addition to these examples, there have also been continuous wavelet transform based filtering circuits implemented using analog circuits to eliminate artifacts from neural data such as heart beat, short spikes, DC offsets and motion.

Digital feature extraction algorithms assume the presence of an on-board ADC that provides sufficient resolution to capture the required information from raw data. Since most of the neural recording applications do not require high bandwidth (less than 10 KS/s per channel), standard Successive-Approximation ADCs remain a popular choice for this category [18,20]. These converters can be implemented to consume low-power while still providing over 10 bits of resolution. Delta-Sigma converters of low orders have also been reported as favorable candidates for biomedical applications [30]. Besides traditional converters, there have been application-specific bio-inspired ADCs mimicking the neuron's inherent pattern recognition abilities [31,32]. The authors report that this neuron-inspired ADC architecture can perform at speeds up to 45 KS/s with less than 1-μW of power consumption.

Digital schemes are the most widely applied and generic signal processing modules applied in medical implants. Digital signal processing comes at low hardware costs and can integrate maximal functionality per unit silicon area occupied especially with scaled technologies. Given that medical implants normally do not demand high clock-speed performance, the digital designs also allow for severe voltage scaling operating in near to sub-threshold regions of operation [33]. In the past, our group has reported a computationally efficient digital implementation of an event-based seizure detection algorithm that can be operated at a voltage as low as 300-mV with less than 350-nW of power consumption per channel [17] (Figure 4). This review intends to focus on digital feature extraction based algorithms besides reviewing hardware techniques to implement the algorithms with minimal computational effort. In epileptic seizure detection, a combination of markers extracted from raw neural data is often used to demarcate seizure from baseline states. The choice of features used to construct an algorithm often decides its feasibility in a battery-powered device. In the next section, we categorize some of the commonly used features to construct seizure detection algorithms based on their detection as well as hardware efficacy. A cost-table is then constructed to quantify the hardware costs of common mathematical operators when implemented using digital circuits. The table may be used as a reference to assign hardware costs based on number of operators used to implement the feature/algorithm, in order to compare two algorithms that may have comparable detection efficacies.

This subsection intends to review some of the basic terminology essential to understanding the issues in evaluating seizure detection algorithms designed for implantable devices. Typically, the detection efficacy of an algorithm or feature is defined by its ability to (i) accurately identify the onset of a seizure and (ii) reject any “seizure-like” short artifacts that could lead to unnecessary stimulation. The former is quantified by a measure of its sensitivity and the latter by specificity. Detection delay is defined as the amount of time after electrographic seizure onset that the algorithm identifies it. There exists uncertainty surrounding the definition of “onset”, and the only current gold-standard is visual inspection by electroencephalography experts trained in reading epileptic patterns. Figure 5 marks out some of these terms with an example algorithm output on animal data. In most cases, researchers use a team of epileptologists to review the data and mark out seizure onsets. Differences in marked onset times are settled by defining onset within a window, rather than a specific time. The uncertainty surrounding the exact temporal definition of seizure onset makes the computation of detection delay (as marked in Figure 5) of algorithms difficult. Literature on seizure spread indicates that seizures could spread to cortical regions from its focus in anywhere from 0–70 s [34]. While it is generally accepted that the efficacy of seizure abatement strategies is increased with an earlier detection, there is no consensus on an acceptable detection delay beyond which therapeutic intervention fails. In the retrospective analysis results discussed in Table 2, detection delay is not taken into account into analyzing the efficacy of the features. As a result of their definitions, false positives and false negatives (a missed seizure) have conflicting requirements, and most designers use an objective cost function to decide detection thresholds for algorithms [35,36].

Another distinction that is important to evaluate the efficacy of an algorithm is its performance in a real-time, look-ahead or prospective study. In other words, using a training set that is different than a testing set would allow for an unbiased evaluation of the algorithm's detection capabilities. Most detection algorithms use some variant of moving windows to average data points to extract features. The size of the window used has a direct implication on detection delay, trading off with false positives and negatives. Recently, Mormann et al. reviewed a comprehensive list of seizure prediction algorithms published in the literature and concluded that not one algorithm showed a performance better than statistical chance when subjected to a look-ahead, unbiased evaluation [37]. The authors encouraged researchers to report percent time spent in false warning, as opposed to absolute number of false positives- as this could be window size dependent. A detailed explanation of the trade-offs involved in setting thresholds, and how they relate to hardware power consumption can be found in [17] and [36].

We compared a set of time and frequency based operators to quantify their ability as markers of electrographic seizure activity. The analysis performed was “retrospective”; without separate training and testing sets. The efficacy numbers obtained using such an analysis reflect the theoretical best case performance of these features and give the designer an idea of what features to select to construct an optimal seizure detection algorithm. Table 2 lists the features compared and the results of the comparison. Data from an animal model of human temporal lobe epilepsy (TLE) was used to test the features under study [38]. The features chosen in this comparison reflect a broad spectrum of common mathematical operators, both in time and frequency domains, used to construct detection algorithms. For details on the equations used to implement these features, the reader is referred to the cited publication for each of the features that uses them in an algorithm [25,26,39–43].

For purposes of unbiased comparison, an equal window size of ∼1 s (1526 samples from data sampled at 1.5 KHz) was used to evaluate the features. The animal data was separated out into baseline and seizures (as identified by epileptologists at the IU School of Medicine) and the test intended to quantify the ability of the feature under study to distinguish these two states. It is to be noted that the seizures used were all electrographic-without consideration for whether there were clinical symptoms associated. The difference in mean values during baseline and seizure were calculated for each of the features under study, and the significance of this difference estimated using the t-test. The statistical power of the test was also reported to give the reader an idea of the significance of the difference in means, given the sample size and variance in each data. To help visualize the demarcation between seizure and baseline data for each feature, we fitted the values into a normal distribution, and calculated the area of overlap between the baseline and seizure fits. A smaller overlap indicates a better demarcation between the two states-indicating the ability of the feature to better separate these two states and vice-versa. Figure 6 shows an example of the normal fit curves for the autocorrelation feature, with the area of overlap shaded. Detection delay is not taken into account for the retrospective analysis, as this analysis is only intended to serve as a preliminary “best-case” indicator of the ability of a specific feature to demarcate baseline from seizure states. A detection algorithm is then constructed using a combination of one or more of the features, per the requirements of the application.

The results from the comparison (Table 2) do not indicate a strong advantage to using frequency based features to identify seizures. However, these features may prove to be powerful tools when used in combination with other time-based features, and have been successfully used to this effect in the past [31]. An important dimension that is not captured by this comparison is the hardware cost associated with each of each of the features. Given that designers often use a combination of features to construct an algorithm, it is important to consider the hardware costs of each feature and weigh the decision of choice of features based on a combination of detection and hardware efficacy. To address this gap, we recently compared a set of time-based detection features on a two-dimensional design space with both detection and hardware efficacies taken into account [36]. The hardware costs associated with each of the detection features was estimated by implementing their simplified mathematical functions using standard VHDL techniques on the IBM90nm CMOS process. This two dimensional space (shown in Figure 7) allows for designers to evaluate the pros and cons of each of the features to construct an algorithm for a battery-powered device. In the figure, a lower number for algorithm efficacy implies a better performance, per the definition of the term used. For details on the techniques used to obtain this design space and hardware implementations followed, the reader is referred to [36].

The features with higher detection efficacies also came with a higher associated hardware cost. Table 3 lists a set of common mathematical operators used to realize hardware implementations for seizure detection features, and a normalized estimate of average power consumption. The normalized power consumption numbers were obtained by implementing the architecture using standard digital circuits on the TSMC65 nm CMOS process. The cost table may be used to make back-of-the-envelope calculations to estimate the hardware cost of a digital feature under study based on the number of each of the listed operations required.

For example, an algorithm requiring using spectral analysis (any of the frequency based operators compared in Table 1) would require the hardware implementation of either FFT or DWT processors. If a DIF-FFT implementation were to be adapted, as reported by [44], the number of “multiplier” and “adder” blocks needed are described by Equation 1 for a radix-4 FFT operation. (1) Number of multipliers = 4 × log 4 ( N ) − 1 Number of adders = 4 × log 4 ( N )

In the Equations 1, “N” represents the number of points over which the FFT is calculated. Using a window size of 1024 samples, an FFT operation can be estimated to use 19 multiplier and 20 addition blocks, amounting to ∼362× from the cost table.

On the other hand, implementing a discrete wavelet transform operator (DWT) allows for a much finer time and frequency resolution at a lower hardware cost than traditional FFT or STFT operations for large windows of data. Recently, we reported a DWT-based detection algorithm implemented on silicon with multiplier-less filters, that demonstrates for optimal detection performance at a low hardware cost [45,46]. There have also been numerous reports on the utility of using wavelet transforms (both discrete and continuous) for detection epileptiform activity [47–49].

The data presented in Table 3 indicates the approximate hardware costs associated with common mathematical operators used in implementing seizure detection features/algorithms. In this section, we present examples of optimizations from the literature applied to mathematically simplify common operators to allow for low-power hardware implementation.

Approximations made to the algorithm or feature under study is another level of design abstraction that can reduce hardware costs of digital features. While this kind of design modification is very application specific and hard to generalize, there have been published reports in the past employing such techniques to minimize hardware power consumption. Reviewing the results of the two-dimensional comparison study presented earlier and in [36], it is evident that the features with higher detection efficacies also consumed higher power. In the study, a simple seizure detection algorithm was constructed by linearly combining the best performing feature (Hjorth variance) with the lowest-costing feature (Coastline/Line length) to study the impact of this combination on the same 2D space [36]. The Hjorth variance feature is mathematically described by Equation 5, and involves the application of two multiplier blocks in its architecture—one for evaluating (Σx)² and another to evaluate x². In the Equation 5, “i” refers to the index of the data point (x) in the k^th window of size “W” with a mean “μ”. (5) Variance ( k ) = 1 W k x ∑ i = 1 W ( x [ i + ( k − 1 ) x W ] − μ k ) 2

The Equation 5 was modified to use the mean of the previous window “ μ_k−1” instead of the present window “μ” and it was observed that this change did not affect the detection efficacy of the feature significantly However, the hardware implementation required to realize this equation now only requires one multiplier (to evaluate square of differences) as opposed to two in the original implementation. The results indicate a 27% decrease in hardware power due to the approximation [36]. Figure 10 captures the location of the Hjorth variance feature before and after approximation on the 2D design space.

Another example of an algorithmic approximation to facilitate simple hardware implementation aims to estimate the dominant frequency of neural data by calculating the time between spike thresholds, or “events” [17]. Most frequency based operators aim to measure the dominant frequency or rhythms present in a window of data to use as a marker of electrographic seizures. The “event-based” seizure detection algorithm proposed in [17] approximates a measure of the dominant frequency by digitizing the time interval between two successive amplitude crossings, or spikes. In digital circuits, this is easily implemented by using a counter and combinational logic to control its clocking and resetting. Figure 11 shows a block diagram of the hardware used for conceptual extraction of dominant frequency from a spike train of data.

The approximation is subject to the correct amplitude threshold being set to ensure the spikes are not missed by the comparator- reducing its robustness and mathematical accuracy with any variations in this threshold with time. However, with adaptive spike thresholding techniques that have been proposed in the past, it is possible to constantly adapt the threshold with changing DC levels of raw neural data [24] (Figure 3). If the frequency of the clock used to increment the binary counter is known, it is possible to accurately estimate the dominant frequency present in the spike-train, and average the same over time to account for temporal instabilities or variations.

Implantable medical devices usually do not have high impositions on throughput (typically operating under 1-MHz), allowing for aggressive supply voltage scaling (V_DD). Figure 12 shows power versus throughput plot for a 5-tap finite impulse response (FIR) filter implemented on a predictive 90 nm technology, as reported by Raychowdhury et al. [54]. The plot quantitatively describes the choice of operating voltage depending on the application space, which is often set by the computational speed (throughput) requirements. As discussed earlier, it is well understood that a higher V_DD results in higher dynamic and leakage power (Figure 14). In addition to V_DD scaling, technology scaling also helps to achieve lower power, providing the benefit of smaller devices and hence, lower capacitance which results in lower dynamic power and area. Figure 13 shows the simulation results of an inverter driving another inverter, illustrating power scaling at iso-performance using scaled technologies. Contrary to common intuition, process scaling, in addition to aggressive voltage scaling also benefits low-frequency applications just as much as high-performance designs. The supply voltages used to quantitatively describe the benefit associated with technology scaling reflect the absolute minimum possible for operating a simple circuit (inverter-driving-inverter) chosen by the authors, it is to be noted that typical operating voltages chosen by designers for low-power digital systems may be higher than projected by the illustration. In traditional medical implants where the chip power is dominated by analog components (due to lack of significant signal processing on board), supply voltages of the order of 2.5 V and greater are commonly seen. The benefits of technology scaling are maximized when the supply voltage is also scaled, sometimes requiring designers to operate digital parts of the implant at near to sub-threshold supplies.

Operation in the sub-threshold region results in increased susceptibility of circuits to process variations, making it imperative to employ circuit techniques to counter the adverse effects of process variations on circuit functionality, power and performance. Moreover, due to the low frequency operation of the system, leakage energy becomes dominant over dynamic energy. Leakage reduction techniques need to be used to achieve overall reduction in the energy consumption of the system. In the subsequent sub-sections, we review such design techniques in detail. A discussion on the optimal V_DD choice for the system for minimum power or energy operation is presented, with relevance to implantable biomedical applications. The following sub-section documents some important considerations for choosing the operating supply voltage for low-power medical applications.

In this sub-section, we briefly review some of the block level circuit designs proposed to reduce either active or leakage energy consumption. While some of the techniques discussed also find broader application from a system-level design abstraction, others help in realizing low-power computational blocks optimized for lower throughput application platforms such as medical implants.