A simple synchronous digital circuit consisting of two sequentially-adjacent registers with a combinational circuit between these registers is shown in Figure 4.

The first register is referred to as launching register whereas the second register is called capturing register.

Two inequalities should be satisfied for this circuit to function properly [25]. Referring to Figure 4, the first inequality is (1) T Cf + T CP ≥ T Ci + T D + T S   where T_Ci and T_Cf are the delay for the clock signals to arrive, respectively, at the launching and capturing registers. Note that T_Ci and T_Cf are also referred to as, respectively, the delay of the clock launch path and clock capture path. T_CP is the clock period. T_D is the data path delay consisting of the clock-to-Q delay of the launching register, logic delay of the combinational circuit, and the interconnect delay. T_S is the setup time of the capturing register. Note that (1) determines the maximum speed of the circuit, making this inequality important for critical paths.

The second inequality that needs to be satisfied is (2) T Ci + T D ≥ T Cf + T Hwhere T_H is the hold time of the capturing register. This inequality guarantees that no race condition exists, i.e., the data is not latched to the final register within the same clock edge. Note that (2) is relatively more important for those timing paths where the data path delay is small, i.e., short paths, such as a shift register or counter.

These inequalities, the type of data path (short versus long), and the type of register (launching and capturing) play an important role in the design of low leakage, dual-V_th registers, as described in Section 4. The timing constraints of a register and related circuit level issues are described in the following section.

Inequalities (1) and (2) require a difference called a skew to be larger than or equal to a timing constraint. These inequalities, therefore, can be rewritten as [25] (3) Setup skew ≥ T S (4) Hold skew ≥ T Hwhere the setup skew and hold skew are, respectively (5) Setup skew = T Cf + T CP − ( T Ci + T D ) (6) Hold Skew = T Ci + T D − T Cf Note the important difference between setup-hold skews and setup-hold times: Setup and hold skews refer to any time difference between the data and clock signals whereas the setup and hold times refer to the minimum required time difference to reliably capture and store the data.

Transistor level realization of a widely used master slave type, edge triggered register is illustrated in Figure 5.

According to the setup time constraint, the data signal should be stable at the input of a register for a sufficient amount of time before the active edge of the clock signal. In the example shown in Figure 5, the active edge is a low-to-high transition of the clock signal since the data propagates to the output after this transition. Setup time guarantees that the data is reliably latched to the master before the rising edge of the clock signal arrives. Ideally, the data signal should propagate through TG1 and INV1, arriving at the output of INV1 before the rising edge of the clock signal. According to this condition, the path that determines the setup time consists of TG1 and INV1, as depicted in Figure 5. This condition, however, may require a relatively large setup time. A conventional technique to characterize the setup time constraint of a register is to examine the setup skew versus clock-to-Q delay relationship, as shown in Figure 6(a) [25–27].

The smallest setup skew that corresponds to the nominal clock-to-Q delay is approximately equal to the summation of the two delays: TG1 and INV1. As the setup skew is further reduced, clock-to-Q delay gradually increases since for smaller setup skews, the data signal cannot reach to the output of INV1. After a specific point, the clock-to-Q delay starts to exponentially increase due to a race condition at node r since this node is simultaneously driven by two gates: TG1 and TG2. The race condition occurs between the new data driven by TG1 and old data driven by TG2. This region is referred to as metastable and therefore avoided during the characterization process. Typically, a 10% degradation in clock-to-Q delay is allowed while characterizing the setup time, as shown in Figure 6(a).

According to the hold time constraint, the data signal should be stable at the input of a register for a sufficient amount of time after the active edge of the clock signal. This constraint is due to non-ideal characteristics of TG1 as a switch. If the hold time constraint is not satisfied, the new data can be latched into the register and overwrite the previous valid data during the same clock cycle. Note that hold time can sometimes be smaller than zero. In this case, even if the new data propagates through TG1, a race condition exists at node r between the new and old data. If the old data succeeds over the new data, the register works correctly and the negative hold time is valid. The hold time constraint is therefore partly determined by the relative drive strengths of TG1 and TG2. Note that, if the hold time is further reduced, the clock-to-Q delay exponentially increases, as shown in Figure 6(b). Similar to setup time characterization, a 10% degradation in clock-to-Q delay is allowed while characterizing the hold time.

These timing constraints (setup and hold times) and clock-to-Q delay play an important role in the design process of low leakage, dual-V_th registers. When specific transistors within a register are replaced with high-V_th devices to reduce leakage current, the timing constraints may change. Ignoring this effect may produce timing violations, causing a degradation in clock frequency or functional failure. The proposed methodology overcomes this limitation, as described in the following section.

The type of timing path and register should be considered during the design process of a dual-V_th, low leakage register. Consider, for example, a launching register in a noncritical or short path. In this case, clock-to-Q delay of the register is not critical and therefore can be traded to reduce leakage current. Similarly, for a a capturing register in a noncritical or short path, (2) is the important inequality and the setup time of this register is not critical. Setup time therefore can be traded to achieve low leakage in a capturing register of a noncritical or short path. Existing techniques cannot utilize this opportunity since the transistors located along the clock-to-Q delay and setup path are realized with low-V_th devices. Finally, consider a capturing register in a critical path. In this case, the hold time is not critical since (1) is the important constraint. Hold time therefore can be traded to achieve low leakage in a capturing register of a critical or long path. Additional constraints, however, exist for each of these three cases to guarantee that both (1) and (2) are satisfied after specific transistors are replaced with high-V_th devices.

Three different types of dual-V_th registers are proposed depending on the type of data path and register, as summarized in Table 1 and described in the following:

This register is designed to replace launching registers in noncritical or short paths. Since there is excessive setup slack in noncritical paths, the primary objective is to trade clock-to-Q delay for leakage current. Both setup and hold times of the register, however, should remain the same (or be reduced) since this register behaves as a capturing register for the previous data path, which may be a critical or short path. Thus, to guarantee that the timing characteristics of the previous path are not affected, the setup and hold times of the register should not increase.

This register is designed to replace capturing registers in noncritical or short paths. Due to excessive setup slack, the primary objective is to trade setup time for leakage current. The clock-to-Q delay of the register, however, should remain the same (or be reduced) since this register behaves as a launching register for the following data path, which may be a critical path. Furthermore, the hold time should also remain the same (or be reduced) since for a short data path, (2) is critical. Note that this second register is sufficiently effective to reduce leakage current since the setup time is relatively more important in advanced technologies, as shown in Figure 7. According to this figure, starting 22 nm technology, setup time of the register is higher than the clock-to-Q delay. Thus, the opportunity to trade setup time for leakage current should not be overlooked. Note that the setup time has been characterized using the procedure described in Section 3.2.

The third register is designed to replace capturing registers in critical paths. The primary objective is to trade hold time for leakage current since in a critical path, (1) is important and hold slack is typically large. The clock-to-Q delay should remain the same (or be reduced) since the register behaves as a launching register for the following data path, which may also be a critical path. Furthermore, the setup time should also remain the same (or be reduced) since for a critical path, (1) is important.

An edge triggered D type flip-flop with 2X drive capability is chosen from an industrial standard cell library. The transistor level schematic of the register is illustrated in Figure 8, including the W/L ratios of each transistor.

Note that in the master latch, a tristate inverter is used that combines the TG1 and INV1 of Figure 5. Similarly, the feedback of the master latch also utilizes a tristate inverter. This schematic and W/L ratios are used in the simulations without any modification.

In the original version, the register shown in Figure 8 is designed using only low-V_th transistors. To design Register 1, high-V_th devices are used for those transistors located along the clock-to-Q delay path, i.e., M13, M14, M17, M18, M19, M20, M21, and M22. Clock-to-Q delay is therefore traded to reduce leakage current. Note that, the setup and hold times of the register remain the same since these transistor do not affect the timing constraints of the register.

To design Register 2, high-V_th transistors are used only for M2 and M3 to trade setup time for leakage current. Note that M5 and M6 are designed using low-V_th transistors even though this inverter is along the setup path, as illustrated in Figure 5. However, as described in the previous section, clock-to-Q delay and hold time of the register should remain the same. Replacing M5 and M6 with high-V_th transistors affects the clock-to-Q delay since this inverter drives the input of the slave latch.

Finally, to design Register 3, high-V_th transistors are used for M7, M8, M9, and M10 to trade hold time for leakage current. Note that the feedback path becomes weaker due to high-V_th transistors. As such, hold time increases since it is more difficult for the old data to overwrite the new data at the output of the first gate, thereby requiring a larger hold time constraint. Low-V_th devices are used for the remaining transistors to guarantee that the clock-to-Q delay and setup time remain the same. For example, M1, M2, M3, and M4 directly affect the setup time constraint and therefore designed with low-V_th transistors. Threshold voltage assignment of all of the transistors are listed in Table 2 for each register.

The amount of reduction in the leakage current achieved by utilizing the proposed three registers is evaluated in this section. Four CMOS technology generations, 45 nm, 32 nm, 22 nm, and 16 nm, are considered using a predictive technology model [28,29].

The register illustrated in Figure 8 is simulated for each technology node where the W/L ratios of the transistors are maintained constant. The leakage current drawn from the power supply is evaluated for the three registers and the results are compared with the leakage current of the original register where only low-V_th transistors are used.

The results are illustrated in Figure 9. Note that for the first register, the state of the clock signal does not change the results since all of the high-V_th transistors are within the slave latch. For the second and third registers, however, high-V_th transistors exist within the tristate inverters. The state of the clock signal is therefore important in evaluating the results. For example, for the second register, clock signal should be at V_SS to guarantee that the initial tristate inverter is not in the high impedance state. Similarly, for the third register, clock signal should be at V_DD so that the second tristate inverter located along the feedback path is not in the high impedance state. The leakage current of the original register is therefore compared with the first two registers and third register when the clock signal is, respectively, at V_SS and V_DD.

The leakage current increases with technology, exhibiting a large jump in the 16 nm node. A significant amount of reduction in the leakage current, 79% on average, is achieved by the first register since the number of high-V_th transistors is higher, as listed in Table 2. The second register also achieves a considerable amount of reduction in the leakage current, 13% on average and higher below 32 nm technology nodes, since the importance of setup time has been increasing with technology, as depicted in Figure 7. The reduction in the leakage current obtained by the third register is relatively smaller, as further discussed in Section 5. All of the results are listed in Table 3 where the absolute reduction in the leakage current is also provided for each case.

The timing constraints (setup and hold times) and clock-to-Q delay of the three registers are characterized as described in Section 3.2. As listed in Table 4, all of the three registers satisfy the required timing constraints listed previously in Table 1.

Specifically, for the first register, setup and hold times are slightly reduced as compared to the original register whereas clock-to-Q delay increases, on average, by 24.6 ps to improve the leakage current. The required condition is therefore satisfied since the setup and hold times do not increase. For the second register, setup time increases, on average, by 13.3 ps to reduce the leakage current. Alternatively, clock-to-Q delay remains the same whereas hold time is reduced, thereby satisfying the required condition. Note that the hold time is reduced since M2 and M3 are high-V_th transistors in this register. It is therefore more difficult for the input data to propagate to the output of the first tristate inverter, requiring a shorter hold time. For the third register, setup time and clock-to-Q delay remain approximately the same whereas hold time increases, on average, by 1.7 ps to reduce the leakage current. The last register therefore also satisfies the required timing constraints.

Three ISCAS 89 benchmark circuits, s27, s526, and s1423, are utilized in this section to better evaluate the efficacy of the proposed methodology on functional circuits rather than only on a register [30]. The total number of gates in these sequential circuits is, respectively, 8, 141, and 490 whereas the total number of registers is, respectively, 3, 21, and 74.

First, the leakage current of the circuits is analyzed when the registers are designed only with low-V_th transistors. In the second step, registers within each sequential circuit is replaced with the proposed registers based on the type of timing path. Since the critical paths are typically a small percentage of the overall circuit, Register 1 and Register 2 can be effectively utilized to trade, respectively, clock-to-Q delay and setup time for leakage power. In the last step, the methodology proposed in [17–19] is evaluated by replacing the low-V_th transistors along the feedback path of a register (M7 to M10, M15, and M16 in Figure 5) with high-V_th transistors. The overall reduction in leakage current is compared for each case in four different technologies. Note that the register illustrated in Figure 5 is used for all of the circuits. Predictive device models are used for each technology [28,29]. The analysis is performed using H-SPICE [31].

The results of the analysis are listed in Table 5.

As summarized in this table, the proposed methodology achieves a significant reduction in the overall leakage current. Average reduction over three circuits and four technologies is approximately 23%. Note that the overall reduction in the leakage current increases as the size of the circuit grows and the ratio of the number of registers to the overall number of gates increases. Also note that according to these results, the reduction achieved by the methodology described in [17] is negligible due to two reasons: (1) As illustrated in Figure 5, the feedback path of the master latch consists of a tristate inverter. Leakage current in a tristate inverter is significantly less than a regular inverter due to increased impedance between the power supply and ground; (2) The feedback path of the slave latch consists of only a transmission gate. The results provided in [17] assume a different register architecture, as shown in Figure 8. For this architecture, there is an inverter along the feedback path of both master and slave latches, thereby increasing the overall reduction in leakage. In this work, the register is chosen from an industrial cell library without any modification. Note that the proposed methodology achieves a higher reduction in leakage current as compared to [17] even for the register shown in Figure 8 since the number of high-V_th transistors is higher in the proposed dual-V_th registers. Also note that the effect of high-V_th transistors on setup and hold times is not considered in [17]. This effect can be significant since an unexpected increase in the setup or hold times can produce a timing violation, as described in Section 4.2.