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Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.

Low power consumption is nowadays paramount for digital integrated circuits. High-performance chips such as multi-core processors for servers are power constrained by the die temperature limit and by both the cooling and electricity costs [^{3} [_{target}_{dd}_{cycle}_{target}_{dd}_{dd}

Ultra-low-voltage (ULV) operation was proposed in the 1970s [_{dd}_{t}_{on}_{dd}_{cycle}_{cycle}_{sw}_{leak}_{cycle}_{leak}_{dd}I_{leak}_{cycle}_{min}_{min}_{min}_{sw}_{leak}_{leak}_{L}

Along with this ULV trend, new CMOS technology nodes have been introduced to maintain the historical increase in on-chip device density. Unfortunately in nanometer CMOS technologies, reaching _{min}

The pitfalls of nanometer ULV circuits limiting their minimum _{dd}

The detrimental impact of stand-by periods on energy efficiency;

The proposed techniques to overcome these limitations.

We specifically target 65 and 45 nm CMOS nodes as they share many characteristics: multiple process flavors, std-

The paper is organized as follows. In Section 2, we recall the impact of CMOS technology scaling on ULV circuits and set up a framework for evaluating energy-efficiency under robustness and timing constraints. We then address the impact of these constraints on the minimum ultra-low _{dd}_{dd}

CMOS technology scaling driven by Moore's law increases MOSFET density on a chip by a factor of two every 18–24 months. This is particularly useful for increasing the functionality of CMOS circuits without increasing die area and thereby by keeping manufacturing costs acceptable. It also boosts speed performances at each technology generation while reducing the energy required to perform a given function [_{sw}_{L}_{on}_{t}

However, CMOS technology scaling also comes with severe drawbacks when reaching nanometer CMOS nodes: leakage currents including subthreshold _{off}_{on}/I_{off}_{t}_{min}_{min}_{t}) within a versatile yet standard CMOS technology menu with good speed performances and negligible area penalty [_{min}

Beyond _{min}_{min}_{dd}_{target}_{cycle}_{target}_{limit}_{dd}_{target}_{target}

R1 region where _{sw}_{dd}

R2 region where _{leak}_{dd}

R3 region where _{leak}_{dd}

Within this framework, it is obvious that _{min}_{min}_{cycle}_{min}_{min}_{leak}_{cycle}_{min}_{target}_{min}_{dd}_{min}_{target}_{min}_{cycle}_{min}_{min}_{min}_{cycle}_{min}_{target}_{min}

As the minimum-energy point (_{min},f_{min},E_{min}_{target}_{cycle}

Finally, let us introduce here that statistical MOSFET variations in nanometer CMOS technologies due to random dopant fluctuations, line edge roughness, oxide thickness variations, etc. have an important impact on energy efficiency. Indeed, these variability sources induce local within-die random _{t}_{on}_{off}

A guardband on _{cycle}_{dd}

Increase in functional limit _{limit}

Increase in mean leakage _{leak}_{leak}_{t}

It has further been reported that _{sw}_{sw}

As shown in _{dd}

The first constraint on minimum _{dd}_{cycle}_{target}_{target}_{min}_{min}_{target}_{t}_{t}_{on}_{0}_{g}_{t}_{th}_{DIBL}_{t}_{leak}_{dd}_{leak}_{leak}_{t}_{0} parameter is compensated by the shorter critical path delay and thus _{cycle}_{D}_{0}_{t}_{min}_{min}_{min}_{target}

Standard nanometer CMOS technologies feature a versatile technology menu with several process flavors targeting different applications: General-purpose (GP) also called generic (G) process targets high-performance applications with short gate delay and relaxed leakage constraints while low-power (LP) process targets portable applications with relaxed speed and tight leakage constraints [_{t}_{on}_{dd}_{t}_{0} reference current. _{dd}_{t}

We thus showed in [_{min}_{min}_{target}_{t}_{min}_{target}_{t}_{t}_{t}_{min}_{t}_{on}_{t}_{target}_{t}_{min}_{target}_{dd}

As MOSFETs in ULV circuits operate in the near- or sub-threshold regime, not only their _{off}_{on}_{t}_{0} parameter from Equation (1). Gate delay is thus very sensitive to _{t}_{cycl}_{e} guardband to ensure sufficient timing (parametric) yield regarding the _{target}_{on}_{t}_{cycle}_{dd}_{t}

Although local variations have a strong impact on gate delay as mentioned in Section 2, the consequence on speed performances is smaller than the effect of global process/temperature variations. Indeed, gate delay variability is averaged out over the high number of gates in critical paths [_{cycle}_{g}

In order to limit _{cycle}_{cycle}_{target}_{dd}_{t}_{min}._{dd}_{dd}_{sw}

When _{dd}_{on}_{on}_{off}_{t}_{dd}_{limit}_{limit}_{limit}_{limit}_{min}

A convenient way to evaluate noise margins of ULV logic was proposed in [_{ih}_{il}_{ol}_{oh}

In order to reliably operate at _{min}_{limit}_{t}_{leak}_{t}

We showed in [_{limit}_{g}_{g}_{gates}_{gate}_{g}_{g}_{g}_{limit}_{L}_{g}_{leak}

As ULV logic features a magnified sensitivity against local _{t}_{cycle}_{dd}_{limit}

We further showed in [_{t}_{limit}

Although this problem can be addressed by upsizing the width or length of MOSFETs within the clock tree, it comes with _{sw}_{L}

To validate this technique, we measured _{limit}_{limit}

Many ultra-low-power applications such as data logging in environmental [_{cycle}_{cycle}_{duty}_{duty}_{cycle}

To mitigate the _{cycle}_{leak}_{t}_{t}_{dd}_{t}_{min}_{target}_{t}_{dd}_{min}_{cycle}_{t}_{t}_{t}_{t}_{leak}_{leak}_{duty}

Therefore, a sleep-mode leakage reduction technique is preferred. Amongst them, power gating relies on the addition of a high-_{t}_{cycle}_{sleep}_{wake-up}_{cycles}_{cycles}_{cycle}_{duty}_{duty}_{cycles}_{dd}_{sleep}_{dd}_{cycle}_{li}_{mit}_{dd}_{leak}_{leak}

In order to limit this noise margin degradation, we showed in [_{t}_{t}_{leak}_{leak}

Ultra-low-voltage (ULV) operation between 0.3 and 0.5 V leads to minimum-energy consumption at the expense of speed for ultra-low-power applications. However, ensuring robust and energy-efficient ULV operation in nanometer CMOS technologies raises a number of design challenges due to high short-channel effects, leakage currents and variability of these technologies. In this paper, we reviewed these challenges and the potential circuit solutions, as summarized in

First, we set up a general framework for analyzing energy efficiency under timing and robustness constraints for the whole range of target clock frequencies _{target}_{t}

We then reported that the frequency of the minimum-energy point _{min}_{target}_{cycle}_{t}_{min}_{target}_{target}_{cycle}

We then analyzed how the minimum supply voltage for functionality _{limit}

We finally analyzed the impact of stand-by periods on effective _{cycle}_{limit}

Maximum clock frequency _{clk}_{cycle}

Minimum _{dd}_{cycle}vs_{target}_{leak}

Measured speed for different CMOS flavors and _{t}

Distribution of maximum frequency with process and temperature variations (measurements of 251-stage ring oscillators with FO1 inverters [_{g}

Minimum _{dd}

Noise margin distribution of ULV logic (SPICE simulations of NAND2/NOR2 gates [

Functional yield at 0.3 V with a 20 mV constraint on minimum noise margin (SPICE simulations of NAND2/NOR2 gates in 45 nm LP CMOS technology, at 25 °C, 50 k Monte-Carlo runs with 95% confidence interval plotted).

_{limit}_{limit}

Impact of stand-by periods on effective energy per cycle _{cycle}

Degradation of noise margins with sleep transistor sizing (SPICE simulations of an 8-bit multiplier for the leakage reduction [

Design challenges for robust and energy-efficient ULV operation under timing constraints in 65/45 nm CMOS technologies.

Challenge | Circuit consequence | Preferred solution |
---|---|---|

Mismatch between _{target}_{min} |
_{cycle} |
Process flavor & _{t} |

Operation at −40 °C | Delay increase—_{cycle} |
Adaptive voltage scaling |

Degraded noise margins | Soft and hard errors—_{limit} |
Upsized _{g} |

Variability-induced clock skew | Hold time violations—_{limi}_{t} increase |
Single-stage clock bufferization |

Long stand-by periods | Effective _{cycle} |
Power gating with opt. sleep transistor |

Dr. Bol is with UCLouvain as a postdoctoral researcher from the National Foundation for Scientific Research (FNRS) of Belgium. Chip manufacturing was supported by the Walloon region of Belgium under TABLOID and E.USER projects. The author would like to thank C. Hocquet from UCLouvain for his precious help with chip measurements.

_{t}