Low power consumption is nowadays paramount for digital integrated circuits. High-performance chips such as multi-core processors for servers are power constrained by the die temperature limit and by both the cooling and electricity costs [1]. Portable applications such as smart phones obviously have an even tighter power budget for battery life concern, which drove innovation during the last decade in advanced power management techniques [2]. Besides these mainstream designs stands another chip category: ultra-low power circuits for applications such as RFID, biomedical devices and sensor networks [3]. These application have in common a minute power budget as the circuits should operate either on tiny batteries (<1 cm³ [4]) or harvest energy from their environment [5]: from a few nW to hundreds of μW. Fortunately, these applications feature low-to-medium speed requirements with target clock frequencies f_target from 10 kHz to 50 MHz, depending on the application and circuit topology. These relaxed speed constraints give room for power savings beyond simple frequency scaling or duty-cycled operation. Indeed, the supply voltage V_dd can be scaled down to reduce the energy required to switch on-chip capacitances at each clock cycle E s w ∝ C L V d d 2 as the associated delay penalty is acceptable given the relaxed cycle time T_cycle at low-to-medium f_target. Ultra-low-voltage operation is the extreme case where V_dd is aggressively scaled down to 0.3–0.5 V with potential energy savings above 10× when compared to nominal-V_dd operation at 1–1.2 V

Ultra-low-voltage (ULV) operation was proposed in the 1970s [7,8] and put back in light for digital circuits in 1999 at the Int. Symp. on Low-Power Electronics and Design [9]. When V_dd is reduced to or below the threshold voltage V_t, MOSFETs start to operate in near-threshold or subthreshold regime [8,9]. As the subthreshold I_on current is exponentially dependent on V_dd, the gate delay dramatically increases. As shown in Figure 1, it significantly reduces the maximum clock frequency for digital circuits. The resulting T_cycle penalty also has a detrimental side effect on the total energy per cycle composed by switching and leakages contributions: E_cycle = E_sw + E_leak. Indeed, the leakage energy increases when reaching subthreshold regime as it results from the integration of leakage power over T_cycle: E_leak = V_ddI_leak × T_cycle. There is thus an optimum supply voltage V_min, which minimizes the energy to an E_min level [10], as depicted in Figure 1. The V_min level is often comprised between 0.25 and 0.5 V depending on the ratio between E_sw and E_leak, which varies accordingly to circuit parameters and technology characteristics through total leakage current I_leak, average switched capacitance per cycle C_L, gate delay and number of gates in the critical path [11]. This concept known as the minimum-energy point has received a lot of attention in the research community during the last decade [3,12] with numerous successful ULV chip implementations: microcontrollers for biomedical applications [13,14] for wireless sensor nodes [5,15] as well as dedicated ASICs for biomedical applications [16,17], communication [18], image processing [19,20] or RFIDs [21].

Along with this ULV trend, new CMOS technology nodes have been introduced to maintain the historical increase in on-chip device density. Unfortunately in nanometer CMOS technologies, reaching E_min in practice raises important challenges because ULV operation magnifies the sensitivity of circuits against MOSFET variability, short-channel effects and leakage currents [6,12]. Several design solutions have recently been proposed to reliably operate nanometer CMOS logic circuits at ultra-low voltage under relaxed yet strict timing constraints: gate length upsize [6], process flavor [22] and MOSFET selection [23], circuit adaptation [22] and power gating [24]. In this paper, we provide for the first time a unified review of:

The pitfalls of nanometer ULV circuits limiting their minimum V_dd for functional robustness and timing closure;

We specifically target 65 and 45 nm CMOS nodes as they share many characteristics: multiple process flavors, std-κ oxide/poly-Si gate stack and strained-Si, which give similar behaviors at ultra-low voltage as shown in Figure 1. To illustrate the findings, we combine chip measurements in 65 nm and simulation results in 45 nm. The results are based on the work carried out in this field at UCLouvain and more specifically on papers [6,22,24,25].

The paper is organized as follows. In Section 2, we recall the impact of CMOS technology scaling on ULV circuits and set up a framework for evaluating energy-efficiency under robustness and timing constraints. We then address the impact of these constraints on the minimum ultra-low V_dd: the speed limit and the functional limit in Sections 3 and 4, respectively. Existing solutions are also presented. Section 5 finally deals with the impact of stand-by periods on energy efficiency, given these constraints on minimum V_dd.

CMOS technology scaling driven by Moore's law increases MOSFET density on a chip by a factor of two every 18–24 months. This is particularly useful for increasing the functionality of CMOS circuits without increasing die area and thereby by keeping manufacturing costs acceptable. It also boosts speed performances at each technology generation while reducing the energy required to perform a given function [26]. ULV circuits for ultra-low-power applications similarly benefit from these enhancements. Indeed, E_sw is effectively reduced thanks to lower on-chip capacitances C_L while gate delay at ultra-low voltage is improved thanks to a higher subthreshold I_on current resulting from the scaled V_t [12]. This leads to boosted speed performances at the minimum-energy point.

However, CMOS technology scaling also comes with severe drawbacks when reaching nanometer CMOS nodes: leakage currents including subthreshold I_off current and gate tunneling leakage [27], short-channel effects [27] and variability [28]. The impact of these nanometer MOSFET effects are magnified at ultra-low voltage [12]. A first consequence at device level is a reduction of the effective I_on/I_off ratio due to lower V_t values and short-channel increase of the subthreshold swing and of the drain-induced barrier lowering (DIBL) effect. A major consequence at circuit level is on the minimum-energy level E_min which stopped scaling from 90 nm node and actually increases significantly at 45 nm node because of the combined effects of subthreshold swing, DIBL, gate leakage and statistical variability [29]. Fortunately, this E_min increase can be limited by choosing the optimum MOSFET (medium gate length and low V_t) within a versatile yet standard CMOS technology menu with good speed performances and negligible area penalty [23]. Moreover, fully-depleted Silicon-on-Insulator (SOI) technology can further save 60% of E_min [29] although this technology is not yet commercially available for industrial circuit design.

Beyond E_min scaling trend, a key challenge for ULV circuit design in nanometer CMOS technologies is to reliably operate at the corresponding supply voltage V_min of the minimum-energy point. Indeed, as shown in Figure 2(a), the minimum V_dd for a logic circuit is given by both timing and robustness constraints [6]. Speed must be sufficient to meet the timing constraint associated with the target frequency f_target of the application. The delay of the critical path has to be shorter than the cycle time T_cycle = 1/ f_target. Moreover, even if safe timing closure is achieved, there is a functional limit V_limit on V_dd, which is independent from f_target. We set up a framework for evaluating energy efficiency under timing and robustness constraints in [6], illustrated in Figure 2. This framework shows that the f_target range of ultra-low-power applications can be divided into 3 regions for ULV circuits:

R1 region where E_sw dominates and minimum V_dd is speed limited,

Within this framework, it is obvious that E_min is only reached at one particular clock frequency f_min corresponding to a T_cycle equal to the critical path delay at V_min. f_min is in R1 region as E_leak accounts for 30% of E_cycle at the minimum-energy point. E_min can thus only be reached for one particular target frequency. If f_target is higher than f_min, switching energy is wasted because V_dd is higher than V_min and, if f_target is below f_min, leakage energy is wasted because leakage power is integrated over a prohibitively long T_cycle. For example, E_min of an 8-bit multiplier in a 45 nm LP (Low-Power) CMOS technology is reached at V_min = 0.38 V and f_min = 630 kHz, as shown in Figure 2. E_cycle is within E_min + 10% between 200 kHz and 2 MHz. For f_target outside this range, Figure 2 shows that practical energy under robustness and timing constraints can thus significantly differ from E_min [6].

As the minimum-energy point (V_min,f_min,E_min) varies with technology generations according to technological characteristics [12], there is an optimum CMOS technology node for each f_target that minimizes E_cycle under timing and robustness constraints [12,30]. However, using an older CMOS technology is not optimum regarding die area and thus high-volume manufacturing costs. For this reason, we focus in this paper on techniques to reliably operate ULV logic at the minimum-energy point in 65/45 nm CMOS technologies.

Finally, let us introduce here that statistical MOSFET variations in nanometer CMOS technologies due to random dopant fluctuations, line edge roughness, oxide thickness variations, etc. have an important impact on energy efficiency. Indeed, these variability sources induce local within-die random V_t variations that exponentially affect subthreshold I_on and I_off [31]. The consequences at circuit level are [6]:

A guardband on T_cycle or on the minimum V_dd for sufficient timing (parametric) yield because worst-case delay of critical paths has to be considered given its large statistical distribution;

It has further been reported that E_sw is also statistically distributed in nanometer ULV circuits because local gate delay distribution introduces random glitches with E_sw penalties [32]. However, for the sake of simplicity we do not consider this effect in this paper.

As shown in Figure 2, statistical variability leads to energy penalties. As local variations can hardly be compensated by circuit adaption due to their randomness from a MOSFET to another, it is important to consider statistical variability when designing ULV circuits in nanometer CMOS technologies. In next sections, we review the constraints on minimum V_dd to ensure circuit robustness given this high local variability in nanometer CMOS technologies.

Many ultra-low-power applications such as data logging in environmental [44] or biomedical [5] domains typically operate on a duty-cycled basis with long stand-by. Power consumed in stand-by mode degrades energy efficiency by adding an overhead to the effective energy per active cycle E_cycle [45]. When assuming ideal clock gating for eliminating switching power during stand-by periods, the effective E_cycle can be expressed as [45]: (4) E cycle = E act + E stb = E act + P leak T cycle × 1 − α duty α dutywhere α_duty is the duty cycle i.e., the percentage of time that the circuit spends in active mode. As illustrated in Figure 9, an α_duty of 0.1% increases the effective E_cycle by a factor of 220× at the minimum-energy point.

To mitigate the E_cycle overhead, P_leak can be reduced either with an active-mode reduction technique or with a sleep-mode reduction technique [6]. Active-mode leakage reduction techniques relies on a V_t increase either globally in the whole circuit or selectively in gates from non-critical paths. At ultra-low voltage, a global V_t increase induces an exponential delay increase that requires a subsequent V_dd increase to maintain speed. If the V_t was already properly selected for making f_min meet the f_target of the application as proposed in Section 3, a global V_t assignment will make the minimum V_dd for speed deviate from V_min and in turn increase E_cycle [6]. Moreover, a selective V_t increase in non-critical paths is not efficient at ultra-low voltages because the exponential delay dependence on V_t due to MOSFET subthreshold operation limits the high- V_t assignment to a few logic gates in very short paths [22]. Besides V_t increase, serial operation was proposed in [46] to limit the number of gates and thereby reduce P_leak. This is an efficient technique which comes at the cost of more complex architectural design. In any case, active-mode leakage reduction techniques can only cut P_leak by a factor of 3–10× [6], which is not sufficient with α_duty values below 5%.

Therefore, a sleep-mode leakage reduction technique is preferred. Amongst them, power gating relies on the addition of a high-V_t sleep transistor to cut off the leakage path in sleep mode. The effective E_cycle can thus be expressed as [24]: (5) E cycle = E act + P sleep T cycle × 1 − α duty α duty + E wake − u p N cycles where P_sleep is the leakage power in stand-by mode, E_wake-up the energy required to wake up from sleep mode and N_cycles the number of cycles in active mode between two stand-by periods in sleep mode. Notice that both wake-up and sleep-mode energies are amortized over N_cycles to calculate the effective energy per active cycle E_cycle. For sleep-mode energy, this is done through the (1 – α_duty) /α_duty term, which also corresponds to the ratio between cycles in sleep and active modes. Wake-up energy can usually be neglected when N_cycles is high (e.g., above 80 cycles in [24]). As in nominal-V_dd operation, the sleep transistor introduces a series resistance on the supply rails, which degrades ULV logic delay [45]. Sizing the sleep transistor thus results from a trade-off between large P_sleep reduction for narrow sleep transistors and small delay overhead for wide sleep transistors. Indeed, the delay overhead need a subsequent V_dd increase to meet the speed constraint with a subsequent E_cycle penalty [45]. Moreover, we showed in [24] that the series resistance of the sleep transistor also reduces noise margins of ULV logic. The consequence on V_limit for functional robustness is even worse than on minimum V_dd for speed. Figure 10 shows the impact of the sleep transistor sizing on P_leak reduction and the noise margin degradation at 0.35 V. A P_leak reduction by a factor of 100× reduces the noise margins by more than 50%, which makes ULV logic prone to functional failures. The impact of the sleep transistor on noise margin should thus carefully be addressed when designing a power-gated ULV circuit.

In order to limit this noise margin degradation, we showed in [24] that standard-V_t (SVT) MOSFETs with an upsized gate length should be preferred as they usually shows better subthreshold characteristics than high-V_t MOSFETs in 65/45 nm LP CMOS. As shown in Figure 10, this optimum sleep transistor in 45 nm LP CMOS degrades the noise margins by less than 20% for a P_leak reduction of 100×. These results with optimum sleep transistor further show that power gating is much more efficient than dynamic reverse body biasing in ULV circuits with long stand-by periods as dynamic reverse body biasing only enable 10× P_leak reduction [6].

Ultra-low-voltage (ULV) operation between 0.3 and 0.5 V leads to minimum-energy consumption at the expense of speed for ultra-low-power applications. However, ensuring robust and energy-efficient ULV operation in nanometer CMOS technologies raises a number of design challenges due to high short-channel effects, leakage currents and variability of these technologies. In this paper, we reviewed these challenges and the potential circuit solutions, as summarized in Table 1.

First, we set up a general framework for analyzing energy efficiency under timing and robustness constraints for the whole range of target clock frequencies f_target in ultra-low-power applications. We specifically took the impact local V_t variations into account in this framework through statistical circuit simulation.

We then reported that the frequency of the minimum-energy point f_min can significantly differ from f_target with large E_cycle energy penalties. Process flavor and V_t selection in a versatile yet standard CMOS technology menu can be used to operate at the minimum-energy point under the timing constraint of the considered application, i.e., make f_min meet f_target. We investigated the impact of global process/temperature variations on the timing constraint set by f_target. Low-temperature operation was shown to be a primary concern as it dramatically degrades delay and thereby involves large cycle time T_cycle guardbands. Adaptive voltage scaling was shown to be able to fix this at reasonable energy penalty.

We then analyzed how the minimum supply voltage for functionality V_limit is set by degraded noise margins and variability-induced clock skew. The first phenomenon induces soft errors due to increased noise sensitivity and even hard errors due to “stuck-at” faults. This can be fixed by gate length upsize and restriction of the logic gates within the standard-cell library to only low fan-in gates. The second phenomenon can lead to hold time violations and can be addressed by single-stage bufferization in the clock tree.

We finally analyzed the impact of stand-by periods on effective E_cycle. Application with low duty cycles need a leakage reduction technique to reduce leakage power in stand-by mode. Power-gating technique is preferred thanks to its high leakage power reduction capability. However, the addition of the sleep transistor harms noise margins and thereby increases V_limit. This side effect can be effectively mitigated by the choice of an optimum sleep transistor.