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J. Low Power Electron. Appl. 2011, 1(1), 1-19; doi:10.3390/jlpea1010001
Review

Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

ICTEAM institute, Université catholique de Louvain, Place du Levant 3, Louvain-la-Neuve, Belgium
Received: 23 November 2010 / Revised: 18 January 2011 / Accepted: 21 January 2011 / Published: 25 January 2011
(This article belongs to the Special Issue Selected Topics in Low Power Design - From Circuits to Applications)
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Abstract

Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.
Keywords: digital CMOS circuits; ultra-low power; subthreshold logic; variability; leakage currents; yield digital CMOS circuits; ultra-low power; subthreshold logic; variability; leakage currents; yield
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).
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Bol, D. Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS. J. Low Power Electron. Appl. 2011, 1, 1-19.

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