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This paper introduces the key elements of a novel low-power, high precision localization system based on Time-Difference-of-Arrival (TDOA) distance measurements. The combination of multiple localizable sensor nodes, leads to an

Indoor local positioning systems have become very popular in recent years. Similar to the evolution of wireless communication systems, the variety, functionality and performance of indoor localization systems are increasing. A wide field of usability in medical, industrial, logistics, transportation systems and collection of geo information is possible (

Illustration of the possible application of the sensor system.

Although high performance is a key element, low power consumption of the systems is even more appreciated. In order to reach the power efficiency goals, new system architectures and components for the sensor nodes are necessary. The presented work focuses on the demand of small and low power sensor systems for

Localization systems based on Global Navigation Satellite Systems (GNSS) such as GPS are well known and have penetrated our daily life. These systems reach their limits when operating indoors or when higher localization accuracy is required. In these scenarios applications can benefit from the use of wireless sensor nodes with localization capability.

Illustration of wireless sensor network with possible applications.

Linear frequency modulation of a continuous wave signal is an ideal approach to localization in wireless sensor networks. This system concept allows a precise localization with moderate circuit complexity. For integration of radar systems in a modern semiconductor technology, a FMCW radar approach is much more suitable compared to a pulse radar based approach. With modern deep sub-micron silicon technology, the maximum achievable output power of the transmit signal is limited. Thus the ratio of the maximum to the average transmission power is a critical system parameter. This ratio is considerably greater in FMCW systems than in pulse radar systems. As a result, a much greater range for the same maximum transmit power is reached. A low-power implementation of the RF circuitry and the analog signal processing is feasible for FMCW systems. Furthermore, a significantly higher spatial resolution compared to pulse radars with the same circuit complexity is possible. The digital signal processing and the detection of individual objects is performed with a Fast Fourier Transform (FFT) and is therefore also realizable with low cost and low power consumption in an integrated circuit.

The core component of the FMCW system is the frequency synthesizer, which generates the necessary frequency ramps. The instantaneous output frequency of the transmitted signal _{0} and the slope

For distance calculation between the nodes the transmitted and the received signals are mixed. The frequency difference is directly proportional to the distance between the sensor nodes.

For position determination by means of the Roundtrip-Time-of-Flight (RTOF) or the Time-of-Arrival (ToA) method, the fixed baste stations (BS) and the mobile stations (MS) must be synchronized with each other. The higher the required accuracy, the greater the demands on the synchronization of the time bases for all participants. The used TDOA method has the advantage that only the BS must be synchronized with one another. No synchronization takes place between the MS and the BS or among the MS. The MS sends out a signal which is received by several BS. One BS serves as a reference node for all other. For position determination the absolute time-of-flight is not necessary. Instead, the difference of the time-of-flight between the _{i}_{i}_{i}_{Offset}_{i}_{i}_{offset}

The calculation of the time difference t_{12} between BS 1 and BS 2 is based in the measured times _{1} between BS 1 and MS and from _{2} between BS and MS 2. Since all BS are synchronized, the offset _{Offset}

The synchronization between the fixed nodes relies on the work presented in [

The following system focuses on an active sensor node with localization ability at 24 GHz with a chirp bandwidth of 250 MHz. The high bandwidth has the benefit of an increased precision and less susceptibility to multipath effects compared to the 2.45 GHz [

The focus of the presented system (

Besides the efficient algorithms for the calculation of distance, this research focuses on high precision front-end components with high system integration in combination with low power consumption. The applied FMCW based Fractional-N synthesizer concept is less power hungry compared to conventional Direct Digital Synthesizer (DDS) based systems. The classical synthesizer concept for precise FMCW frequency ramps relies on a DDS circuitry for ramp generation. This block delivers the time varying reference frequency for an integer-N PLL. The PLL acts as a frequency multiplier. In our concept a fixed reference frequency is used. The frequency chirp is solely generated by a continuous variation of the frequency divider values, which is controlled by a digital ∆Σ-modulator and an additional finite state machine. The DDS in the classical concept has a power consumption of about 400 mW. It is replaced with the mentioned digital circuitries which only need 2 mW from a 1.5 V supply rail. Due to this, the power consumption of the FMCW synthesizer is reduced by about 90%.

Schematic of the proposed 24 GHz localization system.

The synchronization between the nodes and the distance measurement is performed by a multi-step approach. Details of the used methodology are shown in [

A synthesizer with a 24 GHz voltage controlled oscillator (VCO) and a phase-locked loop (PLL) is the key element of the sensor node. The 24 GHz VCO is the contribution of a partner in the project consortium. The fractional-N PLL (

Schematic of the proposed 24 GHz FMCW Synthesizer.

The PFD compares the phase and frequency of the divided VCO signal with the reference frequency. Depending on the transitions of the input signals, the PFD generates UP and DOWN pulses, which trigger the charge-pump (CP) current sources.

Schematic of the Phase-Frequency Detector.

The basic charge pump structure consists of two MOS-Transistors as current sources. This concept has matching discrepancies and tolerances during the fabrication of the integrated circuit lead to non-idealities and degrades the overall system performance. Another problem is the clock-feed through of the reference frequency. This problem is especially severe at high reference frequencies above 100 MHz. Both effects lead to increased spurs in the output spectrum of the synthesizer. Only with an improved charge pump design can the expected system accuracy be realized.

The structure of the improved charge pump design is given in _{CP,D} for the cancellation of charge injection [_{CP1} and T_{CP7} are placed at the rails and the transistors T_{CP3} and T_{CP5} act as current sources. The charge compensation transistors between the switches and the current sources compensate the charge injection from the switches into the current sources. An inverse DOWN and UP signal is necessary to drive the compensation transistors. This inverse clock is generated with respect to the PFD delay between the inverted and non-inverted UP and DOWN signals to achieve two non-overlapping clock signals. By use of these transistors, it is possible to significantly reduce the clock-feed through at high reference clock speeds.

Another enhancement of this structure is the use of an operational transconductance amplifier (OTA) to regulate the current mismatch between the UP and DOWN current sources. The OTA is placed in a feedback loop between the output node Y and the reference node X at the input and the gate of the current source transistors T_{CP3} and T_{CP4}. The node X is the reference for the output voltage. The feedback loop ensures that I_{CP4} always equals I_{CP3} and thus also the output current of the charge pump. Thereby it is possible to ensure the same drain-source voltage across the current sources and to minimize the current mismatch between the UP and DOWN sources.

(

The structure of the operational transconductance amplifier is shown in _{B2} in diode connection is used. Other biasing structures are also possible, but for this use a gain variation due to process variations is tolerable [_{Vss} and C_{Vdd} are used to stabilize the gates of the current sources against fast voltage drops due to switching effects. The capacitance C_{miller} is part of the OTA and is necessary to stabilize the feedback loop. By use of a miller capacitance the pole-zero diagram changes and stability over the desired frequency range is assured.

(

If the spurs to be filtered are more than ten times the loop bandwidth, a third order filter can provide additional benefit. Designing a passive loop filter, involves solving for the time constants and then determining the loop filter components from the time constants. The impedance of the loop filter is:

With the time constants _{1}–_{3} and the factors _{0}–_{2} given in [_{2} = _{0} − _{1} − _{3}

The frequency divider has to divide the incoming 24 GHz VCO signal in order to compare it with the reference frequency. The divider structure for the realized PLL consists of a prescaler with a permanent division factor of S = 8 and a multi-modulus divider (MMD) [_{0} + 2^{1}_{1} + … + 2^{n−2}_{n}_{−2} + 2^{n−1}_{n}_{−1})
_{0}, _{1}, …, _{n}_{−2}, _{n}_{−1} are the programmable control bits. Due to the prescaler with static division and the reference frequency of 128 MHz, a MMD with five divide-by-2/3 cells is necessary. A division factor of 16 to 31 in the MMD can be reached with the five controlling bits. The MMD structure is designed in CMOS logic and consumes a total power of 3.4 mW. The prescaler for division from 24 GHz down to 3 GHz was designed in true single phase clock (TSPC) logic [

The most critical part in the divider chain is the first stage, which must operate at the highest input frequency. Speed improvements in digital CMOS circuits are not only achieved by scaling to shorter channel length but also by improved circuit techniques. If there are no constraints in power consumption the use of current mode logic (CML) based dividers is common. The topology of a static divide-by-two circuit in CML is described in [

The TSPC logic is based on the principle of precharging and evaluating stages [

For the proposed designs, an extended true single phase clock (E-TSPC) divider is used instead of the explained TSPC divider to decrease the RC delay and increase the speed of the structure [

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The presented system is tested for localization ability and accuracy, system integration and low power consumption. The first step of verification is the proof of concept. This is performed with a system demonstration based on state of the art system components [

The system of the second generation focuses on miniaturization and power reduction. The synthesizer as the core component of the transceiver can reach a size below 1 cm^{2} with a power consumption of less than 40 mW in total and an expected measurement distance of up to 20 m. The PLL itself only consumes 10 mW due to the new divider concept based on true-single phase clock technique. The divider within the PLL consists of a static CML divider stage followed by TSPC stages and a CMOS multi-modulus divider. The measurement results of the TSPC divider in

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The research leading to these results has received funding from the federal ministry of education and research (BMBF). The authors wish to acknowledge the financial support of the BMBF and also the cooperation of the project partners.

The authors declare no conflict of interest.