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J. Low Power Electron. Appl. 2018, 8(2), 12; https://doi.org/10.3390/jlpea8020012

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

1
Marvell Semiconductor Inc., Santa Clara, CA 95054, USA
2
Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
*
Author to whom correspondence should be addressed.
Received: 29 March 2018 / Revised: 23 April 2018 / Accepted: 27 April 2018 / Published: 30 April 2018
(This article belongs to the Special Issue CMOS Low Power Design)

Abstract

This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics. View Full-Text
Keywords: analog-to-digital converter (ADC); comparator-based asynchronous binary search (CABS) ADC; subranging; successive approximation register (SAR); time-interleaved (TI); hybrid ADC analog-to-digital converter (ADC); comparator-based asynchronous binary search (CABS) ADC; subranging; successive approximation register (SAR); time-interleaved (TI); hybrid ADC
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).
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Zahrai, S.A.; Onabajo, M. Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters. J. Low Power Electron. Appl. 2018, 8, 12.

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