A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention†
AbstractTo minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. View Full-Text
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Hiienkari, M.; Teittinen, J.; Koskinen, L.; Turnquist, M.; Mäkipää, J.; Rantala, A.; Sopanen, M.; Kaltiokallio, M. A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention. J. Low Power Electron. Appl. 2015, 5, 57-68.
Hiienkari M, Teittinen J, Koskinen L, Turnquist M, Mäkipää J, Rantala A, Sopanen M, Kaltiokallio M. A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention. Journal of Low Power Electronics and Applications. 2015; 5(2):57-68.Chicago/Turabian Style
Hiienkari, Markus; Teittinen, Jukka; Koskinen, Lauri; Turnquist, Matthew; Mäkipää, Jani; Rantala, Arto; Sopanen, Matti; Kaltiokallio, Mikko. 2015. "A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention." J. Low Power Electron. Appl. 5, no. 2: 57-68.