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J. Low Power Electron. Appl. 2015, 5(2), 57-68; doi:10.3390/jlpea5020057

A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention

1
Technology Research Center, University of Turku, Joukahaisenkatu 1C, 20520 Turku, Finland
2
Department of Micro and Nanosciences, Aalto University, Otakaari 5A, 02150 Espoo, Finland
3
VTT Technical Research Centre of Finland, Tietotie 3, 02150 Espoo, Finland
4
TDK, Keilaranta 8, 02601 Espoo, Finland
This paper is an extended version of our paper published in IEEE S3S Conference 2014.
*
Author to whom correspondence should be addressed.
Academic Editors: David Bol and Steven A. Vitale
Received: 20 February 2015 / Revised: 8 April 2015 / Accepted: 10 April 2015 / Published: 17 April 2015
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
View Full-Text   |   Download PDF [829 KB, uploaded 20 April 2015]   |  

Abstract

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. View Full-Text
Keywords: timing-error prevention (TEP); Ultra-Low Power (ULP); digital CMOS; clock stretching; near-threshold; variability; energy-efficiency timing-error prevention (TEP); Ultra-Low Power (ULP); digital CMOS; clock stretching; near-threshold; variability; energy-efficiency
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Hiienkari, M.; Teittinen, J.; Koskinen, L.; Turnquist, M.; Mäkipää, J.; Rantala, A.; Sopanen, M.; Kaltiokallio, M. A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention. J. Low Power Electron. Appl. 2015, 5, 57-68.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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