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Usually Wide Dynamic Range (WDR) sensors that autonomously adjust their integration time to fit intra-scene illumination levels use a separate digital memory unit. This memory contains the data needed for the dynamic range. Motivated by the demands for low power and chip area reduction, we propose a different implementation of the aforementioned WDR algorithm by replacing the external digital memory with an analog in-pixel memory. This memory holds the effective integration time represented by analog encoding voltage (

Extending the dynamic range (DR) of a CMOS image sensor’s (CIS) remains one of the challenges to be faced in designing an effective versatile sensor. Improvement of image capture capability can be done either by reducing the noise floor (NF) of the sensor [

Examples of using a digital memory can be found in a large variety of solutions [

Nevertheless, we can find memory free WDR solutions as well. For example, in [

It is especially interesting to look into the free memory solutions in [

With autonomous control over the integration time category, the memory emerges as the main cause for the increase in both the complexity and the cost of the solution. Attempts to dump the memory in this category have been undertaken as well. In [

In this work, we present two novel concepts in “ranging” and analog encoding voltage (

In addition, we present two designs which implement the “ranging” and

The presented work is organized as follows:

The solution we have used for the DR extension is called the autonomous control over the integration time (multiple resets). None of the pixels in this solution are classic 3T’s, because this enables individual pixel reset via an additional transistor [_{pixel}_{pixel}

The bottleneck of the basic solution is that bits representing the

Our solution is based upon “ranging” and

We have divided the WDR algorithm into three phases (

Three Phases of the proposed WDR algorithm.

During Phase 2, the pixel integrates in accordance with its

Digital Pixel Value: Mantissa and the EXP bits.

During Phase 3, both the

The Coarse and Fine Quantization of the Pixel Signal.

In general, the three phases can overlap each other. However, in this study, we present the first version of the algorithm; therefore, we assume that each phase is completely separated from the others. In future works we will demonstrate how these phases can be overlaid on each other. We assessed the duration of each phase in accordance with further presented simulation results. In

How are the values of _{min}. We also decided that the _{min} is derived from the properties of the comparator that are to be employed for assigning the _{min} are intuitive and straightforward:
_{out_comparator}_{offset}

Analog encoding voltage (

After the pixel array has been reset globally, Phase 1 begins. The pixels are exposed to light and accumulate the photo-generated charge. At certain predetermined time points, each pixel row is sampled nondestructively and spanned by a piecewise increasing ramp. In case the pixel signal intersects with the ramp, the comparator flips and the corresponding

Phase 2 performs the conditional resets to the pixel array. Since the base of the DR extension is 2, the integration times are ordered in exactly the same way as in our previous solutions [

Nonetheless, in the current solution, the pixel reset cycle can be reduced by a factor of 2 at least, since the number of operations before the conditional reset is halved. All that has to be done is to compare the individual

Phase 3 concludes the frame. At this stage, the analog pixel value (

For most applications the required dynamic range (DR) does not exceed 120 dBs, so the pixel structure can be straightforward. In our case, all we need is to accommodate the

Schematic of

The functionality of the _{1}_{6}; and the second is responsible for the _{7}_{11}.

The charge transfer from the _{1} or we can transfer the charge for further processing to _{s}_{2}. We use a simple conditional reset scheme, implemented by _{3} and _{4} transistors, to implement the multiple resets algorithm. By activating the _{rst}_{5}, _{6} form a traditional source follower to handle the _{S}

_{7} and _{8}. By activating the _{AEV }_{10} and _{11}. This relatively simple pixel was implemented in layout using 0.18 µm CMOS technology, with 14 µm pitch and 40% fill factor (FF) (

Layout of

Phase 1

After Phase 1 is completed, Phase 2 begins. During this phase, each pixel integrates in accordance to the assigned

Phase 2

In our solution, the pixel is reset as long as its

In a _{row_reset}_{AEV_read}_{compare}_{min_TYPE I}:

Given the minimal integration time, we can easily calculate the maximal possible DR extension factor (DRF) [_{min_TYPE I} is 112 µs. Assuming the maximal integration time is 30 ms, we have obtained a DR extension factor equal to 256 (48 dB). The expected intrinsic DR

In the last phase of the frame (

The

Phase 3

The main difference between the Ultra WDR (

Schematic of

The inputs to this stage are: the pixel integration time represented by _{14}); the photo-generated signal (_{8}); and the global reference signal _{9}). These inputs are sampled from _{AEV}_{S}_{15}) or _{s}_{10}), the differential stage compares the _{11}, controlled by _{b }_{13}), which sets the current magnitude throughout the amplifier branches. To facilitate the power reduction, we inserted an additional transistor _{12} in the series to the current source in order to shut down the entire stage, when no comparison is needed. The load of the _{6} and _{7}. The drain of the latter is connected to the drain of _{4}, forming a self-reset structure.

The self-reset feature of the _{4}) is raised globally, connecting the output of the _{5}. Obviously, when the amplifier’s output is low, the _{s}_{rst}_{s}_{3}), which forces _{5.}

_{17}) selects the appropriate pixels’ row. The _{16}), which is driven by the column-wise common source amplifiers, enables the corresponding _{AEV}

At the end of the frame, both the _{18} and _{19}) and converted by column-wise amplifiers, as will be explained later.

Layout of the

The

The three phases in the _{AEV}_{S}_{AEV}_{AEV}_{AEV}

Phase 1 of

Post-Layout Simulation of Phase 1 of

In the illustrated case, there are four different photo-generated signals, falling within four different segments; therefore every pixel is assigned a different _{AEV}_{AEV}_{AEV}_{AEV}_{min}, which is 0.1 V in this case, and this difference stays intact after the _{AEV}

It is important to understand that the time of the first span is shorter than the minimal integration time, since, during all the spans, the available signal to be accumulated is lower than the pixel swing by 2Δ_{min}. However, during the next phase the entire pixel swing is available, thus the real integration period will be somewhat higher. In the specific example we have discussed, the minimal integration time will be not 100 ns, but rather 112 ns.

Phase 2 in a _{4} to the gate of _{5} (

Phase 2 of

Equation (6), which describes the minimal pixel conditional reset time, sets the minimal integration time and, as such, defines the available DR extension. In this case, the minimal integration times can be set as low as 112ns, which enables the DR to be extended by over five decades.

_{S}_{S}

Post-Layout simulation of: (

The final A/D conversion occurs at Phase 3. We use the same comparator configuration as depicted in _{S}

Post-Layout Simulation of Phase 3 of

In conclusion, the relatively complex structure of the

Another important factor is the examination of the power performance of the

In analyzing the

In

Based on these simulations, we have concluded that the two presented designs consume power of 2.5 nW and 5.4 nW, respectively. Taking into account the anticipated extraordinary DR extension they provide, we have found that the power budget is low and definitely appropriate to the state-of-the art CMOS image sensors [

Power per Pixel Distribution of

To summarize the anticipated performance of the proposed designs, we provide

Comparison between state-of-the art WDR image sensors.

Parameter | [ |
[ |
[ |
[ |
[ |
TYPE I | TYPE II |
---|---|---|---|---|---|---|---|

Technology | 0.18 µm | 0.09 µm | 0.18 µm | 0.35 µm | 0.18 µm | 0.18 µm | 0.18 µm |

WDR T. | Well Cap.Adjustment | Well Cap.Adjustment | Frequency | TFS | Multiple Capt. | Multiple Resets | Multiple Resets |

Pixel Size | 3 µm × 3 µm | 5.86 µm × 5.86 µm | 23 µm × 23 µm | 81.5 µm × 76.5 µm | 5.6 µm × 5.6 µm | 14 µm × 14 µm | 17 µm × 17 µm |

FF | - | - | 25% | 2% | 45% | 40% | 25% |

DR | 100 dB | 83 dB | 130 dB | 100 dB | 99d B | 108 dB | 170 dB |

SNR | 48 dB^{*} |
48 dB ^{*} |
- | - | - | 48 dB ^{*} |
48 dB ^{*} |

PPX | - | 400 nW ^{**} |
250 nW | ≤6.4 µW ^{**} |
10 nW ^{**} |
2.5 nW | 5.4 nW |

FR | - | 30 | - | - | 15 | 33 | 33 |

(^{*}): The SNR was assessed based upon the well capacity of the photo-diode; (^{**}): The PPX was calculated by normalization of total power by the number of pixels within the array.

From

When a new WDR solution is proposed, it is always interesting to compare it to the existing ones and to realize the added value the new solution contributes. In the present discussion, we perform a comparison between the two proposed solutions to the following algorithms: the multiple captures [

First, the multiple captures algorithm must be considered. In this solution, the pixel integrates for several periods of time, regardless of the intensity of the incoming light. After each integration, the intermediate pixel value is synthesized out of both the newly generated and previously stored samples, respectively. At this stage we assume that all the captures are performed in a rolling shutter mode to comply with the minimal memory requirements for this solution. In case multiple captures are performed in a global shutter mode, the memory requirements will be much higher. For a rolling shutter operation mode, the number of memory bits for each pixel equals its digital resolution: _{resolution}_{captures}_{convert}_{read}_{write}

On the other hand, both the previous and newly proposed multiple resets solutions are applied on a global shutter sensor to obtain the maximal possible number of operations. According to the snapshot mode, the number of memory bits for a single pixel equals _{EXP}_{EXP}_{EXP}_{EXP}_{EXP}_{2}_{EXP}_{EXP}

The first term in (8), relates to the sequential generation of DR bits, which consists of memory read, pixel conversion by the comparator, and memory write cycles. The second term relates to the digital readout of the memory contents, and the last term denotes the A/D conversion of the pixel

In the newly presented

The term _{EXP}

Next, we will demonstrate the meaning of Equations (7–9) by substituting the possible values for each parameter. We have presented the results in _{captures}_{EXP}

For the previous solutions of multiple resets, we chose the logarithmical representation as in [_{EXP}_{captures}

The advantage of the multiple captures algorithm is that most of it is implemented in a digital domain and the pixel structure is rather simple. The clear disadvantage is that this solution requires an extensive processing to obtain the final result. From Equation (7), it is shown that the number of operations increases linearly with the number of captures. This fact is clearly demonstrated by

The Comparison of a number of operations for “Multiple Captures”, “Multiple Resets Previous”, and “Multiple Resets New” algorithms.

N_{EXP} = N_{captures} |
|||
---|---|---|---|

N_{captures} = N_{EXP} |
Multiple Captures [ |
Multiple Resets Previous [ |
Multiple Resets New (This Work) |

2 | 21 | 9 | 5 |

3 | 42 | 13 | 6 |

4 | 63 | 16 | 7 |

6 | 105 | 23 | 10 |

18 | 357 | 61 | 25 |

In the multiple resets algorithm, although the pixel structure and the pixel control are more complex than in the first case, the overall processing is much faster, since the pixel adjusts the integration time autonomously during the frame. Thus, there is no need for an extensive post-integration processing—only to combine the data of the

The two solutions, proposed within the current study, bring the number of operations to its minimum, since they completely eliminate the operations related to a digital memory unit. This feature enables the proposed solutions to be the fastest among the three, which have been analyzed in this discussion. The clear disadvantage of the pixel using

We have presented two designs:

Since our algorithm is based upon integration times ordered in geometrical progression, we divide the pixel swing _{pix}_{1}, _{2}_{n}

During the frame, the pixel discharges from the _{pix}_{1} equals 2Δ_{min}. Consequently, the subsequent segments will be equal to 4Δ_{min}, 8Δ_{min}, and so on, till the last segment _{n}

It is important to note that the last segment _{n}_{pix}_{min}. This means that signals exceeding _{n}

That the number of _{n}_{min}, there will be four different segments; thus, four values of

The ramp signal _{pix}_{4} in this case, will be converted. In this way, the ramp starts on its way in the middle of the restricted region marked in red (

Division of the Pixel Swing to Segments.

Conversion of a pixel swing composed out of four segments.

From there, it climbs in geometrically decreasing steps, gradually covering all the pixel segments. To insure that all the segments are duly covered, the ramp _{min}. An additional positive consequence of such ramp configuration is that the minimal SNR during each conversion is set by Δ_{min} (see Appendix B).

Special attention needs to be paid to the synchronization between the change of _{program}_{AEV}

Another essential aspect is the assignment of the _{1} segment. In such a situation, some pixels, found at the lower boundary of a _{1} segment can mistakenly receive

Up to this point, we have explained the aspects of a single pixel span, but what happens if we were to perform additional spans to complete the desired number of _{EXP}_{min} from the pixel lower boundary. If we look for the reason the _{min}. Therefore, these pixels do not receive new

Distribution of the different light intensities by segments (

All the spans are spread non-uniformly in time. The occurrence of each span _{k}_{k} is the MSB that can be encoded in the _{1} = 18; _{2} = 14; _{3} = 10; _{4} = 6; _{5} = 2, respectively. Furthermore, assuming that _{pix}_{min} = 0.112 V; _{int }_{1} till _{5} are: 100 ns; 1.65 µs, 26.4 µs, 422 µs, and 6.75 ms, respectively.

SNR is one of the key properties of every sensor. Every designer must be aware how much noise each specific circuitry architecture generates. Herein, we discuss three noise sources shot noise, flicker noise, and the thermal noise. We consider the noise of the two types of the sensors separately. The performed analysis shows that in poorly illuminated scenes, the thermal noise governs the noise floor for both of the sensors, whereas the shot noise of photo-diode sets the noise limit in highly illuminated scenes. We refer to noise induced to

We assume, for our convenience that all noise sources are uncorrelated, therefore we can write the overall SNR as:
_{n_KTC}_{n_shot}_{n_read}_{ph}_{int}

The noise analysis for this sensor is straightforward, due to its conventional structure. At the beginning of the frame, the in-pixel sense capacitance _{S}_{B}

Shot noise within the photodiode is inflicted by both the dark current _{dc}_{ph}

In case the accumulated charge is maximal, _{pix}

According to our assessments this amount of noise can reach 4 mV. In such a case the maximal SNR according to (16) equals 48 dB.

The readout noise in this sensor is mainly generated by the in-pixel source follower amplifiers, through which the readouts of _{Pix_Out}_{AEV_Out}

It must be noted that there are additional noise sources within the source follower amplifier such as: flicker and telegraph noise [

Additional noise sources, which have to be taken into consideration during the readout, is the thermal noise generated by the column-wise high gain comparator (_{CS_in}_{Diff}

Substituting the corresponding values into (18), (19), we assessed that the input referred noise coming from the comparator is 55 µV, which is substantially lower than the one induced by the source follower.

The in-pixel dynamic capacitance storing _{AEV}_{AEV}_{AEV}_{S}_{min}, we get the following minimal SNR:

For example, if _{AEV}_{min} is 50 mV, we can observe that the minimal SNR is 37 dB, which is enough for obtaining 4–5 bits resolution during each span.

To conclude,

The SNR in this sensor is also given by (13). The first two terms of noise, namely _{n_KTC}_{n_shot}

The noise associated with

_{rms}-Temporal-Noise 82 dB-Dynamic-Range CMOS Image Sensor with a 13-to-19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC