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This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/).

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

The silicon Micro-electromechanical Systems (MEMS) microgyroscope has been developed recently in the automotive industry as a kind of miniaturized angular rate sensor for several applications like rollover detection, inertial navigation, and the electronic stability programs. As is known, it has the merits of small volume, light weight, high reliability and low cost, thus it is easy to digitize and intellectualize and suitable for mass production.

Apart from the micro structure design and vacuum packaging, the readout electronics for this inertial sensors have usually been realized using analog circuit technology by either PCB or ASIC. Considering the investigation on the signal detection and control technology applied in the SMG has significant meaning since it is crucial to improve gyro's accuracy and back-end system integration. Most traditional SMG control and signal detection tasks are implemented only with analog circuits, which are easily susceptible to outer electromagnetic interference with poor device temperature characterization. On the other hand, some intelligent control and signal processing methods can be realized to enhance the stability and flexibility.

Compared with other embedded devices such as Micro-programmed Control Unit (MCU) and Digital Signal Processing (DSP), FPGA is a high performance device integrated with millions of digital logic elements, which can perform more complex numerical computing, logic decision and measuring-control functions even with low power consumption and fast parallel processing. Nowadays, It has been developed into a System on Chip (SoC) integrated device based on a FPGA/DSP hybrid system.

Some mature prototype microgyroscopes have been realized by analog circuit technology [

As can be seen in

The gyroscope structure adopted here is that the drive mode and sense mode are completely symmetric because they are both varying-area style. First, the proof mass is electrostatically driven to single harmonic vibration in drive mode. Then, if the rotation occurs, another single harmonic vibration in sense mode will happen in the perpendicular direction. All the motions can be actuated and sensed through an interdigital combo structure. A detailed schematic has been introduced in our previous work [^{2} type amplitude detector, a low pass filter FIR3, a reference voltage _{ref} to set the vibrating amplitude of the gyroscope and PI controller. The software phase-locked loop (SPLL) is comprised of phase detector, loop filter, a PI controller and numerical control oscillator (NCO). Meanwhile, the varying step least mean square demodulation (LMSD) is implemented by algorithm in sense mode. The detailed operation mechanism will be discussed in the following sections.

As for the key analog interface, there have been a lot of papers discussing it extensively. By experimental comparison, the front end with the ring diode detection is adopted to improve the SNR ratio. The minor signal can be picked up by demodulating the Coriolis effect induced aF magnitude of change in the vibrating capacitance using a high frequency carrier up to 10 MHz and precision integrated ring diode HSM2829 (HP company). Almost all the discrete devices like capacitances and resistances with fine temperature coefficients are adopted by the industrial standard.

Different from the full analog circuit design, apart from the necessary front-end, almost other parts are realized in FPGA. Actually, the analog front-end are similarly adopted in drive and sense modes, and the subsequent digital parts include AGC, SPLL and LMSD are all realized using specific Verilog language in FPGA. Here all the 128 order filter FIR and LPF filters are selected from the Megacore IP library embedded in the software development tools. Besides, to save limited hardware resources, 16-bit fixed-point numbers and algorithms are implemented without decreasing the system precision.

In the traditional analog electrostatically actuated microgyroscope, the 90 degrees phase difference between driving force and vibrating displacement cannot been ensured in the case of the temperature variation. Therefore, there always exits a certain drift for the natural frequency of microgyroscope even though the self-oscillation is working. To solve this problem, in FPGA a closed-loop self-oscillating driving scheme is utilized. Most discrete device parameters are represented as the numerical values stored in FPGA that can be made immune to outer interferences including temperature drift.

Essentially, the microgyroscope should be a linear sensor only responsive to the input angular rate around the input axis. Hence, the driving status must be stable in both amplitude and frequency. To satisfy these two requirements, closed-loop control must be achieved in the actuation of the microgyroscope. One is that the phase angle of the whole closed-loop

The principle of the digital AGC module is shown in ^{2} type amplitude detector to get square term and the DC term. Through another high-order low pass FIR its effective amplitude will then be derived. The error between the actual signal amplitude and expected reference amplitude _{ref} will be calculated. In the PI controller, the error value _{err} will be sent to two branches. One is to calculate the proportional term by multiplying _{P} (proportional coefficient) and the other is to calculate the integral term by multiplying _{i} (integral coefficient) and accumulating the previous results. Next, the key variable gain will be generated using superposition of the proportional term and the integral term. Last, prior to a D/A convertor, the changing drive detection signal
_{gain} to get an adjustable driving signal
_{p}_{i}_{o}_{i}

In drive mode, the driving signal and the displacement detection signal in drive mode are always perpendicular, even though the resonant frequency has a certain drift over temperature. Almost most analog or digital gyroscope circuit systems adopt the PLL technique to sustain the phase difference stability and resonant frequency tracking [_{o}(_{i}(_{e}(_{e}(_{p} and integrated after being multiplied by the coefficient _{i}, which is followed by summation. Especially, adjusting here the loop parameter can improve the overall system performance. The output signal _{c}(_{c}(

Normally in SPLL module, the NCO can be realized by DDS generator [_{0}_{0},y_{0}) in rectangular coordinate system is rotated to the desired vector _{n}_{n},y_{n}) through n times successive regular rotation operations. After n iterations, sin_{i}_{i}_{i}^{−}^{i}_{i}_{i}

Considering each step rotation angle is a primitive set value, _{i}_{i}

In order to realize the shift-add operation, the general gain factor constant _{n}

Another auxiliary variable _{i}

In the rotation mode, the final angle accumulator value _{n}_{n}

Therefore, the final result in rotation mode can be written as

Especially, to get the sin_{0} = 0, x_{0} = 1, then we will find that _{0} = 0, _{0} = 1 and _{0} = 0.

In actual FPGA, by adding, subtracting and shifting operations, the 16-level pipelines structure CORDIC algorithm is easily realized. As for pipeline technology, the shift registers is utilized to insert before each digital adders or subtractors in each level of the module, which aims to avoid the extra time delay in the FPGA implementation of the complex assembly logic circuit. This kind of hardware based on pipeline structure needs total 16 layers of modules, and the inner CORDIC module can be serially cascaded. The shift register in NCO is used to record the corresponding input rotation information of each step. According to this information quadrant, together with the sine and cosine symmetry, the output CORDIC module will be controlled through the control logic module. In this way the input phase range of the CORDIC module can be regulated to ±0.5π, thereby reducing the iteration error and improving the tracking accuracy. Eventually this structure configuration will finally improve the overall system performance.

All simulation blocks in Matlab have been built as shown in

Other important modules like AGC will be implemented using the discrete multiplier, digital filter and PI modules. Besides, some instruments in gray and specific variables in blue for monitoring the real-time key signal nodes are employed to record some useful curves as shown in

Similarly, the corresponding simulation blocks created by DSPbuilder tools can be seen in

Due to fabrication error induced by the stiffness coupling term between the drive and sense modes, apart from the inevitable noise _{cori}_{qua}^{T}·

In Equations (^{T} will converge to a stable vector to make the difference ^{T}·_{cori}_{qua}

As can be seen from

When the step length u is only set to 0.03, the approaching time is short and the divergence magnitude is poor, which demonstrates a strong noise. Whereas if the step length u is only changed to 0.003, the approaching time is longer, but the convergence error becomes smaller than the former. Thus, if we first set u equal 0.03 to improve the approaching rate. After the output signal error approaches a certain range, then we adjust u equal 0.003 to make the divergence error as small as possible. By this intelligent varying step method, we can realize both high-speed and low-noise LMSD method.

As can be seen from

Nearly one hour of detection results of vibrating frequency and amplitude in drive mode are shown in

Similarly, the mean detection voltage value of vibrating amplitude in drive mode is near 1.5803 V, and its variance is 1.45 × 10^{−5} V, thus the stability of both vibrating frequency and amplitude in drive mode have achieved a high precision (the relative error is lower than 1 × 10^{−5}). The testing results demonstrate the stability in drive mode and the high precision detection ability of minor signal in sense mode. With the scale factor of 8.775 mV/°/s in full measurement range of ±300 °/s, the nonlinearity is less than 400 ppm and ZRO (Zero Rate output) is very stable at room temperature. Through the overall temperature range from −40 °C to 60 °C, the maximum scale factor deviates by about 10 percent from the room temperature value, which to some extent verifies the temperature stability in harsh environment. All the experimental results can be seen from

In

Though the FPGA chip has introduced some more current dissipation than that of the analog design, we still think that it is a good method to realize miniaturization. Along with the analog-digital mixed integrated circuit techniques update, the overall power consumption will be greatly decreased using the new developing low power FPGA chip substitute of 28 nm technology with the compatible package. In

When the main clock frequency of more than 100 MHz is adopted, the core dynamic dissipation is increased dramatically, while other thermal power dissipations will not be changed too much. Thus, in order to make the core dynamic thermal power dissipation smaller, only 50 MHz main frequency is adopted in our system. For a lot of clock signals and 300 KHz sampling rate in the digital system, actually it is easy to deploy them by dividing the main frequency.

The performance of the microgyroscope is greatly decided by the measure and control electronics. From many previous researches, there is a general tendency to select digital technology to replace the traditional analog circuit. Considering the faster parallel speed and low power consumption, a digital microgyroscope based on an embedded FPGA is developed. Different from other FPGA system, the fast sampling rate AD converter with enough 18-bit precision is utilized, and advanced algorithms include SPLL and LSMD are successfully simulated and implemented by hardware programming.

In drive mode, the AGC and SPLL modules work in parallel to ensure the real-time self-exciting and phase locking. The AGC module can make the oscillating amplitude of the proof mass stable in a set constant value. Meanwhile, the SPLL module can track the natural frequency over temperature drift by keeping the 90 degree phase difference between the input driving signal and displacement detection signal. Both the Matlab and DSPbuilder simulations based on FPGA are implemented to validate the algorithm function by adjusting the key parameters, which could provide a reference for the following hardware debugging. In sense mode, to avoid the traditional multiplication method, a varying step LMSD is adopted to realize faster and accurate demodulation. All used algorithms are programmed by fixed point numerical computing, which could save a lot of hardware resources of FPGA and greatly lower the power consumption.

A vacuum packaged microgyroscope is inserted in two pieces of printed circuit boards. The final testing results show that the digital microgyroscope based on embedded FPGA has good performance. Especially, this prototype can be further developed to form a Micro Inertial Measure Unit (MIMU) system by only adding another front-end for another sensing structure without changing the digital parts. Besides, the most previous analog devised are replaced by a digital algorithm, thus our FPGA-based digital gyroscope can have better temperature performance in many harsh applications.

The authors gratefully acknowledge the financial supports from Chinese National Science Foundation (Contract No. 61001048), Key Laboratory of Micro-Inertial Instrument and Advanced Navigation Technology, Ministry of Education, China (Project No. KL201102), Major Project Guidance Foundation of Basic Scientific Research Operation Expenses, Southeast University (No. 3222002107), and Natural Science Fund project in Jiangsu Province (BK2012739).

Design scheme of the digital system.

Schematic diagram of digital AGC module.

Schematic of the SPLL module.

Sketch of the CORDIC algorithm. (

Matlab simulation block diagram.

Matlab simulation results.

DSPbuilder simulation block diagram based on FPGA. (

DSPbuilder simulation results with fixed point algorithm.

Schematic simulation of LMSD algorithm.

Varying step LMSD effects.

Experimental setup for drive and sense modes.

Results of amplitude and frequency outputs in drive mode.

ZRO and scale factor of the microgyroscope at room temperature.

Scale factor of the SMG over temperature.

Power dissipation analysis over main clock frequency.

Performance index comparison of analog with digital microgyro prototype.

Performance |
9.6 mV/°/s | 8.775 mV/°/s | |

15 °/h | 12.45 °/h | ||

0.024 °/s/√Hz | 0.01 °/s/√Hz | ||

±300 °/s | ±300 °/s | ||

0.02 °/s | 0.01 °/s | ||

≤400 ppm | ≤200 ppm | ||

Power Supply | ±5 V | ±5 V | |

≤20 mA | ≤30 mA | ||

Environment |
3 °/s | 1 °/s | |

<0.03 °/s/°C | <0.01 °/s/°C |