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Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers
Automation and Systems Research Institute (ASRI)/Inter-university Semiconductor Research Center (ISRC), School of Electrical Engineering & Computer Sciences, Seoul National University, Seoul, Korea/Daehak-dong, Kwanak-gu, Seoul 151-019, Korea
Department of Electronic Engineering, Chungnam National University, Gung-dong, Yusung-gu, Daejeon 305-764, Korea
* Author to whom correspondence should be addressed.
Received: 12 October 2010; in revised form: 10 November 2010 / Accepted: 15 November 2010 / Published: 24 November 2010
Abstract: In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g~389 mV/g, the output nonlinearity of 0.43% FSO~0.60% FSO, the input range of ±2 g and a bias instability of 122 μg~229 μg. The signal-to-noise ratio and the noise equivalent resolution are measured to be74.00 dB~75.23 dB and 180 μg/rtHz~190 μg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%~1.9% and 0.3%~0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics.
Keywords: design optimization; out-of-plane microaccelerometer; Extended Sacrificial Bulk Micromachining (ESBM) process; CMOS capacitive readout circuit
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Cite This Article
MDPI and ACS Style
Lee, S.; Ko, H.; Choi, B.; Cho, D.-I. Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers. Sensors 2010, 10, 10524-10544.
Lee S, Ko H, Choi B, Cho D-I. Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers. Sensors. 2010; 10(12):10524-10544.
Lee, Sangmin; Ko, Hyoungho; Choi, Byoungdoo; Cho, Dong-il Dan. 2010. "Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers." Sensors 10, no. 12: 10524-10544.