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Electronics 2017, 6(4), 78; https://doi.org/10.3390/electronics6040078

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

1
Laboratory of Systems Engineering, National School of Applied Sciences, Ibn Tofail University, BP 242, Av. de L’Université, Kénitra 14 000, Morocco
2
Laboratory of Electrical Engineering & Telecommunication Systems, National School of Applied Sciences, Ibn Tofail University, BP 242, Av. de L’Université, Kénitra 14 000, Morocco
*
Author to whom correspondence should be addressed.
Received: 31 July 2017 / Revised: 21 September 2017 / Accepted: 25 September 2017 / Published: 4 October 2017
(This article belongs to the Special Issue Hardware and Architecture)
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Abstract

As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical designers and electronic design automation (EDA) providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR). An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP) technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS) and total negative slack (TNS) improved up to 13% and 56%, respectively, compared to the baseline flow. View Full-Text
Keywords: technology nodes; optimization; global route; detail route; wire delay; worst negative slack (WNS); total negative slack (TNS); back-end-of-line (BEOL); non-default-rules (NDRs); self-aligned double patterning (SADP) technology nodes; optimization; global route; detail route; wire delay; worst negative slack (WNS); total negative slack (TNS); back-end-of-line (BEOL); non-default-rules (NDRs); self-aligned double patterning (SADP)
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).
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Darmi, M.; Cherif, L.; Benallal, J.; Elgouri, R.; Hmina, N. Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes. Electronics 2017, 6, 78.

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