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Electronics 2017, 6(3), 69; https://doi.org/10.3390/electronics6030069

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816, USA
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Received: 10 July 2017 / Revised: 15 September 2017 / Accepted: 16 September 2017 / Published: 20 September 2017
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Abstract

The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead. View Full-Text
Keywords: emerging technology; hardware security; logic locking; security metrics emerging technology; hardware security; logic locking; security metrics
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).
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Alasad, Q.; Yuan, J.-S.; Bi, Y. Logic Locking Using Hybrid CMOS and Emerging SiNW FETs. Electronics 2017, 6, 69.

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