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Electronics 2017, 6(2), 46; doi:10.3390/electronics6020046

Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core

1
Faculty of Sciences, LR99ES30 EmE Lab, University of Monastir, Monastir 5000, Tunisia
2
Higher Institute of Applied Sciences and Technology, Department of Electronic Engineering, Taffala City,4003 Sousse, Tunisia
*
Author to whom correspondence should be addressed.
Academic Editor: Mostafa Bassiouni
Received: 30 December 2016 / Revised: 2 June 2017 / Accepted: 7 June 2017 / Published: 19 June 2017
(This article belongs to the Special Issue Cryptographic Hardware for Embedded Systems)
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Abstract

The Elliptic Curve Digital Signature Algorithm(ECDSA) is the analog to the Digital Signature Algorithm(DSA). Based on the elliptic curve, which uses a small key compared to the others public-key algorithms, ECDSA is the most suitable scheme for environments where processor power and storage are limited. This paper focuses on the hardware implementation of the ECDSA over elliptic curveswith the 163-bit key length recommended by the NIST (National Institute of Standards and Technology). It offers two services: signature generation and signature verification. The proposed processor integrates an ECC IP, a Secure Hash Standard 2 IP (SHA-2 Ip) and Random Number Generator IP (RNG IP). Thus, all IPs will be optimized, and different types of RNG will be implemented in order to choose the most appropriate one. A co-simulation was done to verify the ECDSA processor using MATLAB Software. All modules were implemented on a Xilinx Virtex 5 ML 50 FPGA platform; they require respectively 9670 slices, 2530 slices and 18,504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, the proposed design was also implemented on an ASIC CMOS 45-nm technology; it requires a 0.257 mm2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW). Furthermore, in this paper, we analyze the security of our proposed ECDSA processor against the no correctness check for input points and restart attacks. View Full-Text
Keywords: digital signature; hardware architecture; ASIC; optimization; low-area; low-power; embedded systems; security analyses digital signature; hardware architecture; ASIC; optimization; low-area; low-power; embedded systems; security analyses
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Sghaier, A.; Zeghid, M.; Massoud, C.; Mahchout, M. Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core. Electronics 2017, 6, 46.

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