Next Article in Journal
Photonic Structure-Integrated Two-Dimensional Material Optoelectronics
Next Article in Special Issue
A Novel Channel Coding Scheme for RFID Generation-2 Systems
Previous Article in Journal
Energetic Stabilities, Structural and Electronic Properties of Monolayer Graphene Doped with Boron and Nitrogen Atoms
Previous Article in Special Issue
RFID Reader Anticollision Protocols for Dense and Mobile Deployments
Article Menu

Export Article

Open AccessArticle
Electronics 2016, 5(4), 92; doi:10.3390/electronics5040092

Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi 43600, Malaysia
*
Author to whom correspondence should be addressed.
Academic Editors: Michael Sheng and Ali Shemshadi
Received: 30 September 2016 / Revised: 20 November 2016 / Accepted: 28 November 2016 / Published: 16 December 2016
(This article belongs to the Special Issue RFID Systems and Applications)
View Full-Text   |   Download PDF [4203 KB, uploaded 16 December 2016]   |  

Abstract

The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 µm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply. View Full-Text
Keywords: CMOS; C-element; flip flop; low power; RFID; shift register CMOS; C-element; flip flop; low power; RFID; shift register
Figures

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

Scifeed alert for new publications

Never miss any articles matching your research from any publisher
  • Get alerts for new papers matching your research
  • Find out the new papers from selected authors
  • Updated daily for 49'000+ journals and 6000+ publishers
  • Define your Scifeed now

SciFeed Share & Cite This Article

MDPI and ACS Style

Badal, M.T.I.; Reaz, M.B.I.; Jalil, Z.; Bhuiyan, M.A.S. Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag. Electronics 2016, 5, 92.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Related Articles

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
Electronics EISSN 2079-9292 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top