SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform
Abstract
:1. Introduction
1.1. Context
1.2. Related Work
1.3. Objective of the Work
2. Algorithmic Considerations for IoMT Applications
2.1. Need for Image Compression and Encryption
2.2. Approximate Computing for Compression Improvement
2.3. Encryption Improvement
3. Architectural Considerations for IoMT Applications
3.1. Design Flow
3.2. Hardware Description of the Chaotic Generators
3.3. Hardware Setup
4. Edge Computing HW/SW Co-Design
4.1. Hardware Description
4.2. Hard/Soft Co-Design
4.3. Resource Utilization
5. Experimental Results
5.1. Experimental Setup
5.2. Results
5.3. Performance Analysis
6. Conclusions
Acknowledgments
Author Contributions
Conflicts of Interest
References
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Config4 | Config3 | Config2 | Config1 | |||||
---|---|---|---|---|---|---|---|---|
Number | Ratio | Number | Ratio | Number | Ratio | Number | Ratio | |
LUT as Logic | 9053 | 17.01 | 7300 | 13.71 | 5300 | 9.96 | 4912 | 9.23 |
LUT as DRAM | 195 | 6.58 | 195 | 4.11 | 195 | 3.11 | 195 | 2.67 |
LUT as Shift Register | 950 | 520 | 346 | 270 | ||||
Slice Registers | 12,207 | 11.47 | 8766 | 8.24 | 7120 | 6.69 | 6766 | 6.35 |
Muxes | 181 | 0.69 | 176 | 0.67 | 176 | 0.67 | 173 | 0.66 |
BRAM Tile | 20.5 | 14.64 | 16.5 | 11.87 | 12.5 | 8.93 | 7.5 | 5.35 |
DSP48 | 24 | 10.9 | 16 | 7.27 | 8 | 3.63 | 4 | 1.81 |
Config4 | Config3 | Config2 | Config1 | |
---|---|---|---|---|
Clock | 0.056 | 0.05 | 0.044 | 0.041 |
LUT as Logic | 0.03 | 0.02 | 0.02 | 0.01 |
Signal | 0.042 | 0.028 | 0.021 | 0.012 |
Block RAM | 0.028 | 0.021 | 0.013 | 0.007 |
MMCM | 0.117 | 0.117 | 0.117 | 0.117 |
DSP48 | 0.016 | 0.011 | 0.008 | 0.005 |
I/O | 0.038 | 0.038 | 0.038 | 0.038 |
Total dynamic power | 0.00 | 0.00 | 0.00 | 0.00 |
Static power | 0.171 | 0.168 | 0.167 | 0.166 |
Power efficiency | 2.13 × 10−7 | 1.64 × 10−6 |
Distance (m) | Line of Sight | Received Data (byte) | Duration (s) | Quality of Experience (%) |
---|---|---|---|---|
0.5 | Yes | 2,621,144 | 3 | 100 |
0.5 | No | 2,621,144 | 3 | 80 |
3 | Yes | 2,621,144 | 3 | 90 |
3 | No | 2,621,144 | 3 | 80 |
10 | Yes | 2,621,144 | 3 | 90 |
10 | No | 2,621,144 | 3.1 | 50 |
30 | Yes | 2,621,144 | 3.1 | 90 |
30 | No | 2,621,144 | 3.1 | 50 |
50 | Yes | 0 | -- |
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Jridi, M.; Chapel, T.; Dorez, V.; Le Bougeant, G.; Le Botlan, A. SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform. J. Low Power Electron. Appl. 2018, 8, 1. https://doi.org/10.3390/jlpea8010001
Jridi M, Chapel T, Dorez V, Le Bougeant G, Le Botlan A. SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform. Journal of Low Power Electronics and Applications. 2018; 8(1):1. https://doi.org/10.3390/jlpea8010001
Chicago/Turabian StyleJridi, Maher, Thibault Chapel, Victor Dorez, Guénolé Le Bougeant, and Antoine Le Botlan. 2018. "SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform" Journal of Low Power Electronics and Applications 8, no. 1: 1. https://doi.org/10.3390/jlpea8010001