In this work we propose minimizing power consumption of digital receiver depending on the quality of signal received. The version of IEEE 802.15.4-2006 at MHz with DSSS physical layer with OQPSK modulation specifies dB possible variation in the received signal strength. We take advantage of this large variation by designing a power scalable baseband architecture, which adapts itself to the variation in signal and interference levels. The digital section adapts the word length () and sampling frequency (). To make the receiver adaptive and low power, various design techniques are proposed in this paper. The key features of this power scalable receiver are interference detector and SNR estimator (IDSE), variable tap and variable coefficient FIR filter, an adaptivity control unit and an adaptation procedure.

Minimizing power consumption of the receiver has been done by various authors in various ways. Varying of the receiver to minimize power requires varying number of taps in the FIR filter. Authors in [1] have proposed a variable tap FIR filter based on approximate filtering to reduce power. In doing so, authors have demonstrated power reduction by a factor of 10. Besides varying number of taps to save power, we have used minimum resolution coefficients for FIR filters to save power. Author in [2] controls the resolution of analog-to-digital converter (ADC) in receiver and digital-to-analog converter (DAC) in transmitter. The ADC resolution is controlled depending on signal-to-noise and signal-to-interference ratio and resolution of DAC is controlled based on crest factor of modulation scheme. The author has not suggested any way to measure signal-to-noise and signal-to-interference ratio. Authors in [3] have proposed reconfigurable radio for MIMO wireless systems. Authors have emphasized on optimizing number of operations, latency requirements and the architecture of signal processing elements to minimize complexity of the MIMO signal processing. Number of antennas and modulations levels are reconfigurable in the systems proposed in [3]. Adaptive word length control is used to implement an OFDM based low power wireless baseband processing system [4]. OFDM processing essentially consists of filtering, followed by an FFT engine and then an equalization block. The Error Vector Magnitude (EVM) of the received signal is continuously monitored, to adjust the word length. If EVM is above a threshold, the word length is increased to improve precision and conversely, for good EVM (low error rate), the word length is reduced. Our approach for receiver design incorporates controlling the amplitude quantization and sampling frequency depending on the SNR levels and interference presence. Our approach of scaling power by varying and applies the concepts of adaptive signal processing to minimize power. Traditionally, adaptive signal processing is well known for minimizing error of signal processing structures [5], whereas our objective is to minimize power while keeping the error criteria as a constraint in the optimization formulation. An adaptation procedure is proposed to facilitate adaptation in packetized communication.

Now let us look at power consumption numbers in present day communication receivers on CMOS technologies. In [6] authors have reported IEEE 802.15.4 receiver (CC2420 chip) consuming mA when active with V power supply. Low power analog front end design for IEEE 802.15.4 has been proposed in a few papers [7,8] . In [7], authors proposed a front end design in CMOS technology that consumes mW, whereas in a more recent paper the authors in [8] proposed a front end in 90 nm technology that consumes mW when active. Authors in [9] have discussed power consumption of various wireless technology for WPAN applications. As mentioned, authors in [9] say that the power consumption of wireless devices scales with the data rate. Typically, IEEE 802.15.4 receiver consumes mA for Mbps, mA for Bluetooth at Mbps, mA for WLAN at Mbps. Power consumptions in analog and digital portion separately have been reported in some papers. Authors in [10] have reported that baseband of IEEE 802.15.4 consumes mA at V supply ( mW) in m technology whereas the analog portion consumes mA. The authors in [9] have given break up of analog and digital portion of the receiver for UWB. Here analog portion consumes mA compared with mA of digital at MHz.

We start the next section by formulating an optimization problem for minimizing power while varying and for the digital baseband. Following this we explain our approach to minimize power based on this optimization. Section 3 explains the simulation and interference model used in subsequent sections. Section 4 discusses various blocks of the receiver, which are designed to accommodate variable and and to be compatible with adaptation procedure. Section 5 discusses the implementation specific details and dynamic power estimation of the design. Section 6 discusses experimental setup and results from the experimental setup to validate the concepts. Section 7 concludes the paper.

As discussed in previous section, we use simulations to determine the combinations of quantization parameters that guarantee the BER for Equation (2). Thus for each input and interference, we evaluate BER of the receiver for several different settings of and .

The design is coded in verilog HDL. Once pre-synthesis simulations are successful, RTL is synthesized for ASIC and FPGA implementation. The power estimation and comparison is done for ASIC implementation and design validation is done on FPGA platform. For power estimation, it is synthesized in -nm UMC CMOS process for maximum sampling frequency of Msps using Synopsys Design Compiler. The power estimation is done once post synthesis simulation is successful. Synopsys Prime Power is used for estimating dynamic power. Input to Prime Power is the VCD (Value Change Dump) file generated from verilog simulation and the synthesized netlist. The VCD file contains all signal transition that occurred during the simulation. For generating VCD file, input to the simulator are the synthesized netlist, test vectors generated in MATLAB and SDF (Standard Delay Format) file used for synthesis.

Figure 13 shows a quantizer in hardware. For an input with word length N, quantizer shifts the input to right by with sign of the word preserved as shown in Figure 13 for equal to one. By doing this, higher order bits do not see lot of switching when they are processed further in the receiver. There will be activity in the lower order bits of the word. Hence with smaller , there is saving in dynamic power.

Table 1 shows the estimated power for various and combinations for a given under different conditions of interference. Case-I corresponds to the case when there is no interference and only noise is present in the system. Case-II corresponds to the case when there is no interference on the alternate channels and only adjacent interference is present with noise. Case-III is the case where adjacent channels are absent, whereas, alternate channels and noise are present in the channel. In case-IV all interferences are present along with noise. Every and combination in the table satisfies the required BER. The estimated power is also shown for all combinations. The combination of and that consumes lowest power for a particular interference and condition is put into the LUT. Such entries are listed under gray shading. The power is estimated for maximum length packet. Average power () is calculated as follows: (12) (13) is the average power consumption during preamble and SFD. is the average power during data. As shown in Figure 4, is preamble and SFD duration. It is symbol long and data is symbols long. The power spent during synchronization is fixed ( = mW) and depends on and settings for the data duration. In order to have a simple clock generator, the operating sampling frequency () for the design are integer division of Msps. They are , , , , , , , and Msps respectively. As shown in Table 1, the sampling frequencies are quantized to the next higher operating sampling frequency. For, e.g., sampling frequency of Msps is raised to Msps. We can see from the table, maximum power consumed by the design is mW. The lowest power consumed by the design as can be seen from the table is mW, when is Msps and is -bit. At this sampling frequency, there is only one multiplier active in the FIR filter. of 2 Msps means the signal with IF of 3 MHz is under-sampled. In spite of under-sampling and coarsely quantizing (-bit) the signal, specified BER is achieved when is high. Thus we see that saving in power can be approximately seven times when is high and interferences are absent.

Looking into Table 1, when there is no interference (Case-I), the variation in power is from mW to mW. It suggests that even with a high-order interference reject filter in RF chain of the receiver, just by estimation power saving of the order of 5 times is possible. It is evident from the Table 1 that when is very high ( dB), of Msps and of -bit works for all interference condition. Thus inaccuracy in interference detection is tolerable at very high as mentioned in a previous section on IDSE. Since this is the power averaged over the maximum packet length possible, the lowest power values is a function of packet length. The average packet length depends on the application and usage. The power numbers for different packet length can be obtained from Equation (12). One more point to consider while looking at the power numbers is, the numbers do not include the possible power savings that can be obtained from a variable resolution ADC. A variable resolution and variable sampling rate ADC can take advantage of different possible and settings to lower the power consumption.

Table 2 shows break-up of gate count of the design in percentage. Total gate count of the design is approximately K gates. We see that tracking unit has largest gate count. We see that expense of adaptivity and lowering power is % additional gate count of IDSE unit. The design contains approximately % memory elements (ROM). The design has many Baugh–Wooley 2’s complement signed multipliers in it, it is by virtue of many FIR filters in IDSE unit and in data-path. Though synchronization units consume more area as shown in Table 2, average power consumed by synchronization units is very less. Considering this, we realize that adding any component to data-path requires more attention than adding a component to synchronization unit. Finally, Figure 14 shows the power consumption as a function of and , as was discussed while formulating the design problem in Equation (1).

The design is implemented on a Xilinx Virtex-II pro FPGA [23] and is tested with a receiver test setup. The test setup includes Vector Signal Generators (VSG), Oscilloscope, FPGA board, spectrum analyzer and a PC with software as shown in Figure 15(a). Figure 15(b) shows the FPGA board with RF daughterboard. RF daughterboard is made using discrete components and works at center frequency of GHz. Inputs are modulated RF and local oscillator signals. The RF input from signal generator is downconverted to IF and digitized before presenting it to the FPGA board. The FPGA does the further processing in the digital to extract the packet. Packet error and packet loss are measured inside the FPGA. This is done by transmitting a packet with 20 known symbols by triggering the VSG repeatedly. Demodulated symbols are compared with the stored sequence of symbols in the FPGA. The packet error counter (packet_err_count) is incremented with every packet error. For packet loss measurement, number of packet transmitted is counted and compared with the number of sync_succ occurred, i.e., number of time synchronization is achieved.

Figure 16 shows snapshot of the baseband signal after the low-IF to baseband downconverter from the experimental setup. The snapshot is taken from within FPGA using Chipscope [23]. Characteristic of the signal changes midway. First half of the snapshot shows the preamble duration. The signal has high dynamic range during this period, when synchronization and IDSE units are active. Second half of the signal has lesser dynamic range. It is the duration of the packet that contains the data. The data duration shown here is captured when the input to the receiver is 1-bit and sampled at 2 Msps.

Figure 17 shows the amplitude vs. time of the signal during various instances of packet reception. Time is in micro seconds and amplitude is the digitally quantized signal. Figure 17(a) shows the baseband signal with frequency and phase error, corresponding to section labeled “A” in Figure 16. Figure 17(b) shows the baseband signal after frequency and phase error correction, corresponding to section “B” labeled in Figure 16. The signal shown here is very close to the ideal baseband signal inside the receiver, since input noise is low. The signal has very high resolution, as is evident from the smoothness of the sinusoid pulses. Smoother high resolution signals cause more switching and hence consume more power. Baseband signal during sampling frequency and bitwidth transition is shown in Figure 17(c). As can be seen, the smooth sinusoids transform to less dynamic low resolution signal. Content of registers in the datapath is discarded during this period. Figure 17(d) shows the baseband signal during data period of the packet. As evident from the figure, signal has low amplitude resolution and is not as smooth as signals captured in Figure 17(b). Signal shown in figure is captured when input to the digital receiver is -bit and the clock frequency is Msps. The power consumption of the receiver is less when the receiver processes such low resolution (time and amplitude) signal.

Figure 18(a) and 18(b) shows the power break-up of the synchronization and data-path sections. The power is averaged over the maximum packet length. The power break up shown is obtained for equal to 8-bit. As can be seen that power consumption by the synchronization unit is much smaller than the units in the data path as they are “ON” for much shorter duration. Among the synchronization units, the fine time tracking unit consumes the most power as it contains many correlators for estimating the fine timing. In data path FIR filters consume the largest power due to many multiply and accumulate units in it.

Figure 19(a) shows the measured PER vs. for the receiver working at -bit and Msps. From the figure it is seen that the required to meet 1% packet error is around dB. Whereas, from Table 1 it is seen that the minimum required is around dB. As discussed earlier, non-idealities of the RF front end and the experimental setup might be the reason for this difference.

The Figure 19(b) shows the PER vs. when receiver works on its lowest configuration, -bit and Msps. It is seen from this figure that the lowest meeting the error criteria is around dB. Table 1 suggests that it requires around 5 dB of for -bit Msps setting to meet the error specification. The difference can be attributed to the factors discussed above. The packet loss is nearly same in both Figure 19(a) and 19(b). This is because the synchronization section in both cases runs at same settings of and . Though the experimental values differ from the values obtained through simulation, the difference is not very significant from the point of verifying the idea of the power scalable receiver. The experimental results verify the claim that for different signal conditions different setting (, ) of the receiver can be used to minimize power while meeting the error criteria. The design of the receiver proves to be working well to receive the packets with different and settings.

We have proposed a baseband digital receiver design that changes its sampling frequency () and word length () based on interference detection and signal quality () estimation. The approach is based on a LUT in the digital section of the receiver. Interference detector and estimator that suit this approach have been proposed. Settings of different sections of digital receiver changes as and vary. But, this change in settings ensures that the desired BER is achieved. Overall, the receiver reduces amount of processing when conditions are benign and does more processing when conditions are not favorable. A hardware protocol is proposed for packet based communication that facilitates power scalable design. It is shown that the power consumption by the digital baseband can be reduced by % ( times) when there is no interference and () is high. Design is experimentally verified and the proposed fact is established that energy condition of the hardware can be minimized when the signal condition is better.