Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface
AbstractIn spite of the great expectations for epitaxial graphene (EG) on silicon carbide (SiC) to be used as a next-generation high-performance component in high-power nano- and micro-electronics, there are still many technological challenges and fundamental problems that hinder the full potential of EG/SiC structures and that must be overcome. Among the existing problems, the quality of the graphene/SiC interface is one of the most critical factors that determines the electroactive behavior of this heterostructure. This paper reviews the relevant studies on the carrier transport through the graphene/SiC, discusses qualitatively the possibility of controllable tuning the potential barrier height at the heterointerface and analyses how the buffer layer formation affects the electronic properties of the combined EG/SiC system. The correlation between the sp2/sp3 hybridization ratio at the interface and the barrier height is discussed. We expect that the barrier height modulation will allow realizing a monolithic electronic platform comprising different graphene interfaces including ohmic contact, Schottky contact, gate dielectric, the electrically-active counterpart in p-n junctions and quantum wells. View Full-Text
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Shtepliuk, I.; Iakimov, T.; Khranovskyy, V.; Eriksson, J.; Giannazzo, F.; Yakimova, R. Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface. Crystals 2017, 7, 162.
Shtepliuk I, Iakimov T, Khranovskyy V, Eriksson J, Giannazzo F, Yakimova R. Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface. Crystals. 2017; 7(6):162.Chicago/Turabian Style
Shtepliuk, Ivan; Iakimov, Tihomir; Khranovskyy, Volodymyr; Eriksson, Jens; Giannazzo, Filippo; Yakimova, Rositsa. 2017. "Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface." Crystals 7, no. 6: 162.
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