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Crystals 2017, 7(6), 162; doi:10.3390/cryst7060162

Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface

1
Department of Physics, Chemistry and Biology, Linköping University, Linköping SE-58183, Sweden
2
CNR-IMM, Strada VIII, 5 Zona Industriale, Catania 95121, Italy
*
Author to whom correspondence should be addressed.
Academic Editor: Helmut Cölfen
Received: 1 May 2017 / Revised: 30 May 2017 / Accepted: 31 May 2017 / Published: 2 June 2017
(This article belongs to the Special Issue Integration of 2D Materials for Electronics Applications)
View Full-Text   |   Download PDF [12621 KB, uploaded 23 June 2017]   |  

Abstract

In spite of the great expectations for epitaxial graphene (EG) on silicon carbide (SiC) to be used as a next-generation high-performance component in high-power nano- and micro-electronics, there are still many technological challenges and fundamental problems that hinder the full potential of EG/SiC structures and that must be overcome. Among the existing problems, the quality of the graphene/SiC interface is one of the most critical factors that determines the electroactive behavior of this heterostructure. This paper reviews the relevant studies on the carrier transport through the graphene/SiC, discusses qualitatively the possibility of controllable tuning the potential barrier height at the heterointerface and analyses how the buffer layer formation affects the electronic properties of the combined EG/SiC system. The correlation between the sp2/sp3 hybridization ratio at the interface and the barrier height is discussed. We expect that the barrier height modulation will allow realizing a monolithic electronic platform comprising different graphene interfaces including ohmic contact, Schottky contact, gate dielectric, the electrically-active counterpart in p-n junctions and quantum wells. View Full-Text
Keywords: graphene; SiC; interface; buffer layer; barrier height; carrier transport graphene; SiC; interface; buffer layer; barrier height; carrier transport
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Shtepliuk, I.; Iakimov, T.; Khranovskyy, V.; Eriksson, J.; Giannazzo, F.; Yakimova, R. Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface. Crystals 2017, 7, 162.

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