VLSI Design of Trusted Virtual Sensors
AbstractThis work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm
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Martínez-Rodríguez, M.C.; Prada-Delgado, M.A.; Brox, P.; Baturone, I. VLSI Design of Trusted Virtual Sensors. Sensors 2018, 18, 347.
Martínez-Rodríguez MC, Prada-Delgado MA, Brox P, Baturone I. VLSI Design of Trusted Virtual Sensors. Sensors. 2018; 18(2):347.Chicago/Turabian Style
Martínez-Rodríguez, Macarena C.; Prada-Delgado, Miguel A.; Brox, Piedad; Baturone, Iluminada. 2018. "VLSI Design of Trusted Virtual Sensors." Sensors 18, no. 2: 347.
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