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Sensors 2013, 13(12), 17265-17280; doi:10.3390/s131217265

Article
Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference
El Hafed Boufouss *, Laurent A. Francis , Valeriya Kilchytska , Pierre Gérard , Pascal Simon and Denis Flandre
ICTEAM Institute—Electrical Engineering, Université catholique de Louvain, Maxwell Building, Place du Levant 3, B-1348 Louvain-la-Neuve, Belgium; E-Mails: laurent.francis@uclouvain.be (L.A.F.); valeriya.kilchytska@uclouvain.be (V.K.); pierre.gerard@uclouvain.be (P.G.); pascal.simon@uclouvain.be (P.S.); denis.flandre@uclouvain.be (D.F.)
*
Author to whom correspondence should be addressed; E-Mail: elhafed.boufouss@uclouvain.be; Tel.: +32-104-725-69; Fax: +32-104-725-98.
Received: 7 November 2013; in revised form: 5 December 2013 / Accepted: 9 December 2013 /
Published: 13 December 2013

Abstract

: This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.
Keywords:
biomedical; high temperature; CMOS subthreshold regime; total ionized dose; ultra-low power; voltage reference

1. Introduction

Silicon circuits are increasingly sought by biomedical applications, such as radiation detectors, breathing sensors and temperature sensors. These applications often require ultra-low power circuits, sometimes also robust to harsh environments. Figure 1 shows our previous development [1] of an ultra-low power microsystem, composed of a temperature sensor, a comparator and a voltage reference. This microsystem aims at temperature sensing in the harsh conditions used in medical sterilization such as high total ionized dose radiation (TID) or high temperature. It has three main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor above T0, and measuring temperatures above T0. The microsystem was developed using a suitable and robust technology, i.e., 1 μm partially-depleted (PD) Silicon-on-Insulator (SOI). Such technology is often used in harsh environments applications because of its attractive features; extended range of working temperature (up to 300 °C), reduced parasitic effects, low-power, high speed and lower sensitivity to transient radiation effects comparing to other technologies [2]. However, during measurements, the voltage reference circuit was the weak point of the microsystem and showed a large shift in the measured reference voltage with radiation of up to 900 mV at 1 Mrad (Si) [3]. To overcome this limitation, a new design of an ultra-low power and harsh-environment immune voltage reference is performed. We firstly choose to port the design to a more suitable SOI industrial technology with Complementary Metal-Oxide-Semiconductor (CMOS) process node of 130 nm featuring a much reduced gate and buried oxides thickness and hence TID degradation [4]. Secondly, we improved the architecture by introducing a cascode bias stage for enhanced stability, and a new start-up design to avoid start deficiency at low temperature and extreme corners (resulting in high Vth). This proposed circuit is optimized to work in the subthreshold regime of the transistors in order to achieve ultra-low power dissipation (less than 100 μW) at high temperature (up to 200 °C).

In this paper, we firstly present the design of the voltage reference circuit. Then, we detail the experimental results of the voltage reference under large range of temperature and under combined high temperature and radiation influence. Lastly, we explain the impact of the combination of high total ionizing dose and high temperature on the proposed circuit and draw conclusions.

2. Basic Concepts

2.1. Voltage Reference Circuit Description

The voltage reference is a CMOS circuit (Figure 2) based on the gate-source voltage difference between a pair of P-type MOS (PMOS) and N-type (NMOS) transistors (Mp and Mn) biased by a proportional to absolute temperature (PTAT) current IREF (Equation (8)). Differently to the initial work described in [5], our design was: (1) improved by introducing a cascode bias stage for enhanced stability and a new start-up design to avoid start deficiency at extreme temperature and process corners (resulting in high Vth); (2) extended to operate in a large temperature range from −40 to 200 °C; (3) conceived to limit the power dissipation in harsh environments, using transistors optimized to work in subthreshold regime.

In the next paragraph, operation of our previous circuit [3] is reviewed, and in the next sections, an improved architecture is proposed.

2.2. Design Principles

From the analysis of the circuit described in Figure 2, the voltage reference value VREF and the bias current IB are obtained as:

V REF = ( 1 + R 1 R 2 ) V GSn | V GSp |
I B = V G S 2 V G S 1 R B
where VGSn, VGSP, VGS1 and VGS2 are the gate-source voltages for transistors Mn, Mp, M1 and M2, respectively. For NMOS and PMOS transistors working in the subthreshold regime, the IV characteristics can be expressed by [6]:
I D n = β n U T 2 exp ( V G S V thn n U T ) [ 1 exp ( V D S U T ) ]
I D p = β p U T 2 exp ( V S G | V thp | n U T ) [ 1 exp ( V S D U T ) ]
where βn = μn.Cox.(Wn/Ln) and βp = μp.Cox.(Wp/Lp), μn,p is the electron and holes mobilities in the channel, Cox is the oxide capacitance per unit area, Vthn and VthP are the threshold voltages of NMOS and PMOS respectively, Wn (Wp) and Ln (Lp) are the channel width and length for NMOS (PMOS), respectively. UT = kB.T/q is the thermal voltage (kB is the Boltzmann constant, q the elementary charge and T the absolute temperature), n is the subthreshold slope parameter, VGS and VDS (VSG and VSD) are the gate-to-source and drain-to-source voltages respectively for the NMOS (PMOS) transistor. For |VDS| > 4UT, the drain current ID becomes almost independent of the drain-to-source voltage [7], so that from Equations (3) and (4) we can extract:
V GSn = n U T l n ( I D n β n U T 2 ) + V thn
| V GSp | = n U T l n ( I D p β p U T 2 ) + | V thp |
In Figure 2, if k is the size ratio (W1.L2/(L1.W2)) of transistors M1 and M2, m the current copy ratio in the output stage (IREF = m.IB) and using Equations (2) and (5), the bias current IB is given by:
I B = n U T ( l n ( k ) R B )
I REF = m n U T ( l n ( k ) R B )

Assuming that the current through the resistances R1 and R2 is negligible and using Equations (1), (5) and (6) we obtain the following expression of VREF:

V REF = n U T [ ln ( β M p β M n ) + M r ln ( n m ln ( k ) R B β M n U T ) ] + ( 1 + M r ) V thn | V thp |
with βMn(p) = μn(p).Cox.(W/L)n(p) for the output transistors Mn and Mp respectively (Figure 2). These β parameters (∝Tα with α ≥ 1.5) together with the parameter n and the threshold voltage Vthn and Vthp have a temperature dependency [8,9]. Mr is the resistors ratio (R1/R2). RB is a non-silicided polysilicon resistance, showing almost negligible temperature dependency in the simulations.

3. Circuit Realization

A new design of the voltage reference (Figure 3) was developed with a cascoded current source, to reduce the VREF variations due to the process corners, supply voltage variation and mainly the radiation effects caused by single ionized particles [10]. As it is based on the same principle as the previous design [3], the voltage reference expression VREF remains unchanged (Equation (9)).

3.1. Design Phases

3.1.1. Technology Characterization at High Temperature

The voltage reference circuit was developed based on the analog MOSFETs of an industrial 130 nm PD SOI CMOS featuring a 5 nm gate oxide thickness and 280 nm minimum length. The SPICE (BSIM3SOI) models available for this technology are commercially validated up to 150 °C. We checked the models validity up to 200°C, by comparing the typical DC ID(VGS) characteristic of a MOSFET transistor extracted by simulations and from measurements for different temperatures (25, 150, 175 and 200 °C). Figures 4 and 5 show two examples of the good agreement between simulated and measured curves, for NMOS and PMOS transistors at 25 °C and 200 °C, in the subthreshold region of interest. The slight discrepancies for the PMOS transistor can be neglected since the circuit design has to cope with much larger variations due to process, temperature and radiations.

3.1.2. Design Optimization

The design optimization consists in determining the bias current IB and the transistor and resistor sizes (in Figure 3) to minimize the VREF variation with the device physical parameters as given by the previous equations and process corners. The temperature dependence of the voltage reference must be as low as possible. The aforesaid dependence is expressed by evaluating the temperature coefficient (TC) defined by the following expression:

[ T C ] = 1 V REF × [ d V REF d T ]

In order to minimize the TC coefficient for our design, we have extracted temperature dependencies of the physical parameters, computed Equation (10) and searched the best design parameters (W1, W2, Ln, m, Mr, Wn, Wp and RB). However this first guess does not take into account the process corners. Next, extensive ELDO (Mentor Graphics) simulations were performed for the different process corners in a temperature range of −40 to 200 °C.

3.2. Design Robustness Against Radiation Effects

To take into account the variations due to radiation effects, additional constraints were considered as follow:

  • The designed circuit was checked with custom model parameters of transistors including TID effects on transistors [11] (up to 30% mobilities degradation and negative voltage threshold shifts of 100 mV).

  • Using transistors with a body contact to limit the effect of the parasitic bipolar possibly created by radiation [10].

  • Choosing relatively long transistor to assure lower leakage current and lower threshold voltages shift, which may appear as a result of TID and high-temperature effects [2,12,13].

  • The circuit layout is further carried out by paying attention to critical components; thus all matched device pairs were realized by a centroid implementation, including the necessary dummies (Figure 6).

Table 1 gives the bias setting and different dimensions of transistors and resistors used in the proposed voltage reference circuit.

3.3. Simulations Results

Simulations are performed for five different process corners and a custom model parameters of transistors including TID effects, namely:

  • Typ: typical corner (typical |Vth| values)

  • FFA: Fast PMOS and NMOS (min |Vth| values) with minimum resistances values

  • SSA: Slow PMOS and NMOS (max |Vth| with maximum resistances values

  • FSA and SFA: are the crossed cases (fast and slow)

  • RAD: Custom model parameters of transistors including TID effects (30% degradation of the mobility and a threshold voltage shift of 100 mV).

As shown in Figure 7, the reference voltage VREF versus temperature range of −40 to 200 °C gives an average voltage of 1.5 V for Typical corner, with a variation of ±8% over all process corners and temperature/radiation conditions. More specifically, lower |Vth| values lead to a lower VREF at a given temperature according to Equation (9), whereas the temperature dependence depends on the exact balance between the n, UT and the Vth terms.

4. Experimental Results

The main purpose of our voltage reference is to be used in a harsh biomedical sterilization conditions. To validate this feature, first the voltage reference circuit was measured in a large range of temperatures from −40 to 200 °C. Subsequently, other chips have been tested during irradiation at different temperatures, using a small ceramic heater resistor placed under chips. Irradiation was performed at the Cyclotron facility of UCL with Gamma-rays, using a Cobalt source (60Co). The next sections present the measured results for a power supply of 2.5 V.

4.1. Temperature Measurements

The experimental voltage reference generates a mean reference voltage of about 1.5 V (Figure 8) with a variation of about 1%, for the temperature range of −40–90 °C with a temperature coefficient less than 133 ppm/ °C. This increases to 470 ppm/ °C for the large tested temperature range of −40–200 °C with a maximum variation of 10%. The maximum power dissipation is less than 42 μW at the lower temperature of −40 °C, about 50 μW at room temperature and only 75 μW at a high temperature of 200 °C (Figure 9).

The 10% increase of the reference voltage value VREF textitversus temperature can be explained through the increase of the subthreshold current and parameters n, UT and (1/βMn) shown in the Equation (9). The decrease of the absolute values of threshold voltages of transistors Vthn and |Vthp| with temperature [8] helps (but not sufficiently) to limit the increase of VREF value versus temperature. To first order, the power dissipation of the circuit is equal to “VDD.(m+2).IB” and according to Equation (8) is proportional to the term n.UT (∝ n.T). This explains the linear variation with temperature of the power dissipation of the reference voltage (Figure 9).

4.2. Measurements under Combined High Temperature and Radiation Exposure

Six chips were exposed to gamma-rays radiation during one week with a dose rate of 10 krad/h and regularly measured. Two chips were kept at room temperature, two heated at 100 °C during radiation and the last two chips at 200 °C. The voltage reference value remains about the expected voltage of 1.5 V with a maximum increase of ±5% shift for room and 200 °C temperature. At 100 °C the voltage reference value increases with total dose up to 400 krad (Si) and starts to decrease at higher dose (Figure 10). The power consumption of the voltage reference increases with radiation and temperature, except for the highest heating temperature during radiation for which the power remains stable at about 75 μW upon radiation (Figure 11). Similar trends are observed for all measured chips. Similarly to temperature case, we can express the radiation dependencies of the voltage reference circuit. This is about 25 ppm/krad for room temperature up to 1 Mrad (Si).

4.3. Discussion of Measurement Results

In order to understand the effect of the combination of radiation and high temperature on the designed voltage reference circuit, the threshold voltages Vthn,p for the used SOI transistors were extracted in the same conditions (irradiation + temperatures). Gamma-rays radiation is known to result in oxide and interface charges build-up (Nox and Nit). They shift the threshold voltages as (Vthn ∝ (NitNox) and |Vthp| ∝ (Nit + Nox)) and degrade mobilities in transistors [11].

Thus, for PMOS (Figure 12) the absolute |Vthp| value increases with radiation. This effect is amplified at 200 °C due to higher Nit creation. For NMOS transistor (Figure 13), at room temperature, induced Nox charges are dominant (versus Nit) and, therefore Vthn value decreases slightly. At 100 °C a balance between Nox and Nit occurs and keeps a relatively stable value for Vthn versus radiation dose. Nit becomes dominant at 200 °C and leads to an increase of the NMOS threshold voltage with dose.

Then, based on the previous expression of VREF (Equation (9)) and knowing that the parameter n is increased and the carrier mobilities μn(p) are degraded both by radiation and temperature [11,14], we can explain the combined effect of radiation and temperature on the circuit (Figures 10 and 11) as follows.

  • At room temperature: As the shift of threshold voltages of PMOS and NMOS seems to be small, the increase of VREF and the power dissipation can be explained by the increase of the parameter n and the decrease of the mobility μn (∝ to 1Mn) under radiation.

  • At 100 °C: At small dose (less than 400 krad) the same effects as for room temperature occur. For higher dose, the absolute value of the threshold voltage of PMOS increases while the NMOS one remains quasi stable, thus leading to the decrease of the voltage value of VREF and to stabilize the power dissipation.

  • At 200 °C: After an initial decrease of Vthn and increase of |Vthp| which is reflected in a decrease of VREF and the power dissipation, both absolute values of Vthn and Vthp increase under radiation. Thus, they compensate each other in the Equation (9) leading to a stable value of VREF and power consumption.

4.4. Comparison with the State of the Art

Table 2 summarizes the performance of the proposed voltage reference circuit and compares it with results of the literature. When compared to our previous work [3], the new circuit is twice less sensitive to temperature variation and the sensitivity to radiation is divided by more than one order of magnitude thanks to: (1) the suitable SOI technology featuring a reduced oxide thickness (5 nm in this work versus 25 nm in the previous work) which limits oxide charge build-up and hence TID degradation; (2) to the new design circuit performed with reasonable margin for the current consumption.

When compared to literature, the proposed circuit operates in a wider range of temperature −40 to 200 °C and radiation (up to 1 Mrad (Si)) than other solutions. Our circuit proposes a high reference voltage value of 1.5 V with a small current consumption (less than 20 μA at room temperature) and achieves a low temperature coefficient for a similar range of temperature.

5. Conclusions

In this work we demonstrated an ultra-low power voltage reference circuit, designed in the subthreshold regime of transistors, developed to be used in harsh environment such as biomedical sterilization. This circuit was simulated up to 200 °C using our extended MOS models and was shown to consume about 75 μW only at higher temperature. The design was verified to be robust against radiation effects (using custom model parameters) and the voltage reference value very fairly stable over a large range of process corners and temperature variations. To enhance immunity to total dose effects, the layout has been implemented using specific guidelines and a suitable SOI CMOS technology with thin gate and buried oxides. Measurements have shown a fairly correct operation of such ultra-low power circuit for a large temperature range (from −40 °C up to 200 °C) and under a combination of total ionizing dose (up to 1 Mrad (Si)) and high temperature. The threshold voltages Vthn,p for the used SOI transistors were extracted under radiation and temperature. They show a significant increase of the absolute value of PMOS threshold voltage with radiation at high temperature, while for NMOS the threshold voltage value Vthn decreases slightly at room temperature, keeps a relative stable value versus radiation dose at 100 °C and increases at higher temperature 200 °C, depending on the balance between Nox and Nit build-up. The results fairly support the observed VREF and power consumption dependences on temperature and total dose radiation.

This work is supported by the Région wallonne (Skywin Projects S@T and Telecom), and the F.R.S.-FNRS of Belgium. The authors would like to thank UCL Cyclotron facility and D. Spôte for his assistance with temperature setup.

Conflict of Interest

The authors declare no conflict of interest.

References

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Figure 1. Biomedical microsystem adapted from [1].

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Figure 1. Biomedical microsystem adapted from [1].
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Figure 2. Voltage reference circuit adapted from [3].

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Figure 2. Voltage reference circuit adapted from [3].
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Figure 3. Proposed voltage reference circuit.

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Figure 3. Proposed voltage reference circuit.
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Figure 4. Measured and simulated ID versus VGS curves at 25 °C, VDS = 1.5 V, W = 1 μm, L = 0.28μm.

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Figure 4. Measured and simulated ID versus VGS curves at 25 °C, VDS = 1.5 V, W = 1 μm, L = 0.28μm.
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Figure 5. Measured and simulated ID versus VGS curves at 200 °C, VDS = 1.5 V, W = 1 μm, L = 0.28μm.

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Figure 5. Measured and simulated ID versus VGS curves at 200 °C, VDS = 1.5 V, W = 1 μm, L = 0.28μm.
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Figure 6. Final layout of the voltage reference.

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Figure 6. Final layout of the voltage reference.
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Figure 7. Simulated reference voltage VREF versus temperature and process corners.

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Figure 7. Simulated reference voltage VREF versus temperature and process corners.
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Figure 8. Measured voltage reference VREFversus temperature.

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Figure 8. Measured voltage reference VREFversus temperature.
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Figure 9. Measured current consumption versus temperature.

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Figure 9. Measured current consumption versus temperature.
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Figure 10. Measured voltage reference VREFvs TID at different temperatures.

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Figure 10. Measured voltage reference VREFvs TID at different temperatures.
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Figure 11. Measured voltage reference power consumption at 2.5 V power supply, in the same conditions as in Figure 10.

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Figure 11. Measured voltage reference power consumption at 2.5 V power supply, in the same conditions as in Figure 10.
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Figure 12. Measured PMOS voltage threshold vs TID at different temperatures.

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Figure 12. Measured PMOS voltage threshold vs TID at different temperatures.
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Figure 13. Measured NMOS voltage threshold vs TID at different temperatures.

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Figure 13. Measured NMOS voltage threshold vs TID at different temperatures.
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Table Table 1. Voltage references bias setting and devices dimensions.

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Table 1. Voltage references bias setting and devices dimensions.
ParameterDescriptionValue
VDDPower supply2.5 V
IBBias current @ 25 °C2.5μA
(W/L)lSize of NMOS M140 μm/0.5 μm
(W/L)2Size of NMOS M210 μm/0.5 μm
(W/L)3–6Size of PMOS M3,M4,M5 and M610 μm /0.5 μm
(W/L)7–8Size of PMOS M7 and M825 μm/0.5 μm
(W/L)pSize of PMOS Mp200 μm/0.5 μm
(W/L)nSize of NMOS Mn20 μm/1 μm
(W/L)9Size of NMOS M95 μm/0.5 μm
(W/L)stSize of NMOS Mst5 μm/1 μm
RBRB resistor value25 kΩ
R1R1 resistor value50 MΩ
R2R2 resistor value20 MΩ
RstRst resistor value1.5 MΩ
Table Table 2. Performance comparison with similar voltage references described in the literature.

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Table 2. Performance comparison with similar voltage references described in the literature.
ParameterThis WorkPrevious work [3]Leung [5]Malcovati [15]Ivanovic [16]Gromov [17]
Technology0.13 μm SOI1 μm SOI0.6 μm Bulk0.35 μm BiCMOS0.13 μm Bulk
Supply voltage2.5 V5 V1.4 to 3 V1 V1.4 V
Reference voltage (V)1.51.80.3330.541.60.405
Temperature range (°C)–40–200 133 [–40, 90 °C]–40–300 375 [–40, 90 °C]0–1000–80–40–1200–80
TC(ppm/°C)470 [–40, 200 °C]825 [–40, 200 °C]9421290200
Consumption @ 25 °C20 μA2 μA9.7μA92 μA
VREF shift due to radiation (ppm/krad)254261400.68
Irradiation particlesGamma-raysGamma-raysNeutronX-rays
Maximum VREF shift due to Combined effect of temperature and radiation up to 1 Mrad (Si)+10%
Dose Mrad (Si)11144
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