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An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, China
College of Electronic Science & Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China
* Author to whom correspondence should be addressed.
Received: 14 April 2011; in revised form: 30 May 2011 / Accepted: 5 June 2011 / Published: 10 June 2011
Abstract: An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.
Keywords: hall plate; simulation model; non-linear effects; Verilog-A
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Cite This Article
MDPI and ACS Style
Xu, Y.; Pan, H.-B. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates. Sensors 2011, 11, 6284-6296.
Xu Y, Pan H-B. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates. Sensors. 2011; 11(6):6284-6296.
Xu, Yue; Pan, Hong-Bin. 2011. "An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates." Sensors 11, no. 6: 6284-6296.