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Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117, Taiwan
Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei, 117, Taiwan
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Received: 4 August 2011; in revised form: 14 September 2011 / Accepted: 15 September 2011 / Published: 27 September 2011
Abstract: This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize through put of thecomputation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.
Keywords: phase unwrapping; digital holographic microscopy; FPGA; reconfigurable computing; system on programmable chip
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Hwang, W.-J.; Cheng, S.-C.; Cheng, C.-J. Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy. Sensors 2011, 11, 9160-9181.
Hwang W-J, Cheng S-C, Cheng C-J. Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy. Sensors. 2011; 11(10):9160-9181.
Hwang, Wen-Jyi; Cheng, Shih-Chang; Cheng, Chau-Jern. 2011. "Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy." Sensors 11, no. 10: 9160-9181.