Next Article in Journal
Fast CU Division Pattern Decision Based on the Combination of Spatio-Temporal Information
Next Article in Special Issue
Hybrid NOMA Protocol with Relay Adaptive AF/DF Collaboration and Its Modeling Analysis in NB-IoT
Previous Article in Journal
Content and Sentiment Analysis of The New York Times Coronavirus (2019-nCOV) Articles with Natural Language Processing (NLP) and Leximancer
Previous Article in Special Issue
A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

A Novel Fully Digital Feedforward Background Calibration Technique for Timing Mismatch in M-Channel Time-Interleaved ADCs

1
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
2
Microelectronic Equipment Technology Department, University of Chinese Academy of Sciences, Beijing 100049, China
3
Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
*
Author to whom correspondence should be addressed.
Electronics 2023, 12(9), 1965; https://doi.org/10.3390/electronics12091965
Submission received: 28 March 2023 / Revised: 19 April 2023 / Accepted: 19 April 2023 / Published: 23 April 2023
(This article belongs to the Special Issue Advanced Technologies in Digital Signal Processing)

Abstract

:
This paper presents a novel digital background calibration technique for timing mismatches in time-interleaved analog-to-digital converters (TIADCs). We reconstruct and eliminate the timing mismatch based on the theory of timing-mismatch-induced spurious signals in the frequency domain. The proposed compensation algorithm utilizes the conjugate property between spurious signals to achieve low complexity. A coarse-fine correction architecture is adopted to eliminate higher-order time-skew errors. A novel feedforward estimation algorithm based on the correlation of adjacent channels is proposed to extract the time-skew errors. Our proposed calibration technique is suitable for an arbitrary number of channels. The simulation results demonstrate that the utilization of the proposed calibration technique yields significant improvements in both the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The SNDR and SFDR are improved from 55.82 dB and 56.64 dB to 79.92 dB and 105.98 dB, respectively.

1. Introduction

Modern electronic communication systems, such as baseband optical communication and satellite communication receivers, have growing demands for high-speed and high-resolution analog-to-digital converters (ADCs) [1,2,3,4,5]. A TIADC system composed by several slow but accurate sub-ADCs can meet the requirements of communication systems [6,7,8]. However, due to the offset, gain and timing mismatches among the parallel sub-ADC channels, the performance of TIADC has been limited [9,10]. The offset and gain mismatch introduce direct current (DC) and gain product terms, and they can thus be calibrated by adders and multipliers, respectively [11]. Hence, the crucial challenge is to calibrate the timing mismatch that acts as the sample-time error, is dependent on input signal and deteriorates with an increase in input frequency [12,13].
In the analog domain, analog and mixed-signal calibration techniques can relieve the timing mismatch via the variable-delay line (VDL) in a direct way. However, the VDL requires an additional analog circuit and is very sensitive to process, temperature, voltage and thermal noise effects, which are detrimental to calibration performance [14,15,16,17]. In contrast, fully digital calibration techniques have the advantages of high reliability and strong transplantation, while their biggest problem (i.e., digital circuit area) can be addressed by employing a more advanced technology.
Many fully digital calibration techniques have been proposed in previous research [18,19,20,21,22,23,24,25,26]. In Ref. [18], the outputs of TIADC are modulated by the Hadamard matrix to generate the pseudo-aliasing signals. However, this approach only adapts to the TIADC with specific channel numbers, owing to the limits of Hadamard transform. Ref. [19] provides a method that exploits the correlation of the input signal and the mismatch spurs in the frequency domain to eliminate the influence of timing mismatch. Nevertheless, this requires a tremendous amount of filters and massive calculation of inverse discrete Fourier transform (IDFT), leading to an increase in hardware complexity; however, millions of sampling numbers are needed to achieve the convergence condition. In Ref. [21], based on the frequency-shifted and derived basis functions, a calibration method for time-skew errors needs the Hilbert filter to reconstruct the complex signal, resulting in the additional consumption of hardware resources. Furthermore, the feedback architecture [18,20,23,24,25,26] is utilized to make their estimated parameters close to the actual value, but this also brings potential stability issues. To address the aforementioned concerns, we put forward a novel, fully digital calibration technique. We utilize the conjugate property of the spurious signals to avoid the generation of complex signal and reduce hardware complexity. We also propose a new feedforward algorithm to mitigate the risk of feedback-structure-induced non-convergence during the extraction of time-skew errors. It is worth noting that our calibration technique is suitable for any channel’s TIADC system.
The remainder of this manuscript is structured as follows. Section 2 presents a detailed exposition and analysis of the proposed calibration methodology. In Section 3, numerical simulations and experimental findings are portrayed. Finally, Section 4 presents a brief conclusion of the proposed method.

2. The Proposed Timing Mismatch Calibration Technique

In this section, a novel, fully digital calibration technique is proposed to calibrate timing mismatches in an M-channel TIADC system. To streamline the matter, it is assumed that the offset and gain discrepancies have been calibrated. Firstly, we analyzed the TIADC model in the frequency domain to extract the spurious signals. Subsequently, the timing mismatch calibration structure is presented according to the aforementioned model.

2.1. The Model of TIADC in the Frequency Domain

In an M-channel TIADC system, the sampling instances t k of each sub-ADC can be written as [22]
t k = ( n M + k ) · T s
where T s represents the sampling period of the TIADC system and k represents the channel number ( k = 0 , 1 , , M 1 ). The flow chart and the sampling sequence diagrams of the M-channel TIADC system are shown in Figure 1.
However, due to the existence of timing mismatches, the k-th channel transfer function can be written as [18]
H k ( j ω ) = e j ω ( k + γ k )
where γ k denotes the timing mismatch of k-th channel. The block diagram of sampling in an M-channel TIADC is shown in the Figure 2. Therefore, the discrete Fourier transform (DFT) of k-th channel outputs can be written as [18]
Y k j ω = 1 M e j k ω i = 0 M 1 H k j ω 2 π i M X j ω 2 π i M
where X ( j ω ) is the DFT of the ideal input signal. Hence, the outputs of TIADC can be written as
Y ( j ω ) = k = 0 M 1 Y k ( j ω ) = X ^ ( j ω ) + i = 1 M 1 Q i ( j ω )
with
X ^ ( j ω ) = 1 M k = 0 M 1 e j ω γ k · X ( j ω ) X ( j ω )
Q i j ω = 1 M k = 0 M 1 e j 2 π i k M e j ( ω 2 π i M ) γ k C i X j ω 2 π i M
where X ^ ( j ω ) denotes the desired signal, Q i ( j ω ) denotes the spurious signals caused by timing mismatches and C i denotes the modulation coefficient. The spectrum of an M-channel TIADC with timing mismatches is shown in the Figure 3a. Note that Q i ( j ω ) is the amplitude modulation for the frequency shift replication of input signals. If the time skew errors are identical or zero, the output signal of each sub-ADC is identical and Q i ( j ω ) can be eliminated perfectly. Considering the existence of manufacturing differences and changes in voltage or temperature, the timing mismatch γ k is different in each sub-ADC. Thus, the key challenge is to eliminate these spurious signals.

2.2. Timing Mismatch Compensation

From Equation (6), we know that the spurious signals Q i ( j ω ) are associated with X ( j ω ) . Theoretically, if we estimate the γ k accurately, the product of modulation coefficient and frequency shift in ideal input signal C i · X j ω 2 π i M approximately equals Q i ( j ω ) , as shown in Figure 3b,c. Thus, the corrected outputs Y ^ j ω can be written as
Y ^ j ω = Y j ω i = 1 M 1 Q i j ω .
The spectrum of corrected signal Y ^ ( j ω ) is presented in Figure 3d. However, the IDFTs of Equations (4)–(7) are complex-valued signals and we cannot directly handle them in the time domain. To solve the above issue, many reports [19,20,21] exploit the additional filters to structure the imaginary components, but this approach has undoubtedly led to an increase in computational complexity and hardware resource consumption. Hence, we propose a novel compensation algorithm to optimize the calculation process and circumvent the calculation from the imaginary components.
Note that the time-skew errors are usually much less than the sampling period and, for the sake of description, we ignore the presence of higher-order error terms and use the first-order Taylor series to rewrite Q i ( j ω ) , expressed as follows:
Q i j ω 1 M k = 0 M 1 e j 2 π i k / M 1 + j ω 2 π i M · γ k X j ω 2 π i M = 1 M k = 0 M 1 e j 2 π i k / M γ k · j ω 2 π i M X j ω 2 π i M
where j ω 2 π i M is the frequency response of the derivative filter. Similarly, Q M i ( j ω ) can be written as
Q M i ( j ω ) = 1 M k = 0 M 1 e j 2 π ( M i ) k / M γ k · j ω 2 π ( M i ) M X j ω 2 π ( M i ) M = 1 M k = 0 M 1 e j 2 π i k / M γ k · j ω + 2 π i M X j ω + 2 π i M .
Thus, the IDFT of Q i ( j ω ) can be written as
Q i [ n ] = 1 M k = 0 M 1 e j 2 π i k / M γ k e j 2 π i n / M · ( h d [ n ] x [ n ] ) = 1 M k = 0 M 1 γ k ( c o s 2 π i k M c o s 2 π i n M + s i n 2 π i k M s i n 2 π i n M + j s i n 2 π i n M c o s 2 π i k M s i n 2 π i k M c o s 2 π i n M ) · x [ n ]
where h d [ n ] denotes the unit sample response of the derivative filter and x [ n ] denotes the derivative of ideal input signal x [ n ] . Note that when we calculate the IDFT the Q M i ( j ω ) , the terms of the frequency shift parameter in Q M i [ n ] conjugate with the frequency shift parameter in Q i [ n ] . Hence, the IDFT of Q M i ( j ω ) can be written as
Q M i [ n ] = 1 M k = 0 M 1 e j 2 π i k / M γ k e j 2 π i n / M · ( h d [ n ] x [ n ] ) = 1 M k = 0 M 1 γ k ( c o s 2 π i k M c o s 2 π i n M + s i n 2 π i k M s i n 2 π i n M j s i n 2 π i n M c o s 2 π i k M s i n 2 π i k M c o s 2 π i n M ) · x [ n ] .
It can be seen that the real components of Q i [ n ] and Q M i [ n ] are identical and their imaginary components are opposite. Hence, we can use the conjugation between Q i [ n ] and Q M i [ n ] to reduce computational complexity, expressed as follows:
e i [ n ] = Q i [ n ] + Q M i [ n ] = 2 M k = 0 M 1 γ k ( c o s 2 π i k M c o s 2 π i n M + s i n 2 π i k M s i n 2 π i n M · x [ n ] = w i [ n ] · x [ n ]
with
w i [ n ] = 2 M k = 0 M 1 c o s 2 π i k M 2 π i n M · γ k
where e i [ n ] denotes the reconstruction conjugate error pair and w i [ n ] denotes the corresponding coefficient. w i [ n ] is a function of period M and, with a specific number of channels, M, the coefficient in front of the time error can be calculated in advance, which can save hardware resource consumption. It is noted that when M is odd, there are ( M 1 ) / 2 conjugate error pairs in total, whereas when M is even, an extra spurious signal appears in π and the corresponding frequency shift in input signal will not generate imaginary components, expressed as follows:
e M / 2 [ n ] = 1 M k = 0 M 1 γ k e j π k e j π n · x [ n ] = w M / 2 [ n ] · x [ n ]
with
w M / 2 [ n ] = 1 M k = 0 M 1 γ k 1 n + k .
However, the ideal signal x [ n ] and its derivative x [ n ] are not available in the blind calibration technique, so we use the outputs of TIADC y[n] and their derivative y [ n ] to approximate them. Similarly, the second-order error terms possess the same conjugate symmetry, and thus we can also use this to reduce the complexity of the operation. Expanding our previous research [22], a coarse–fine correction method is employed, based on the second-order Taylor series, to eliminate higher-order timing-skew errors. During the initial coarse correction stage, the first-order Taylor series approximation is utilized to correct y [ n ] , expressed as follows:
y c ^ [ n ] = y [ n ] e c [ n ]
with
e c [ n ] = i = 1 < ( M 1 ) / 2 > ( w i [ n ] · y [ n ] ) + w M / 2 [ n ] · y [ n ] e x i s t s w h e n M i s e v e n
where < · > denotes the rounding down operation. In order to mitigate the impact of higher-order time-skew errors, the fine-calibration process employs a second-order Taylor series approximation, expressed as follows:
y f ^ [ n ] = y [ n ] e x [ n ] e x , 2 [ n ]
with
e x [ n ] = i = 1 < ( M 1 ) / 2 > ( w i [ n ] · x [ n ] ) + w M / 2 [ n ] · x [ n ] e x i s t s w h e n M i s e v e n ,
e x , 2 [ n ] = i = 1 < ( M 1 ) / 2 > ( w i , 2 [ n ] · x [ n ] ) + w M / 2 [ n ] · x [ n ] e x i s t s w h e n M i s e v e n ,
w i , 2 [ n ] = 1 M k = 0 M 1 c o s 2 π i k M 2 π i n M · r k 2
w M / 2 , 2 [ n ] = 1 2 M k = 0 M 1 r k 2 1 n + k
where w i , 2 [ n ] and w M / 2 , 2 [ n ] denote the coefficient of the second-order error term.
To improve the accuracy of the approximation and mitigate the impact of higher-order error terms, the output of the coarse correction process, represented as y c ^ [ n ] , is substituted for the first-order derivative of the ideal output x [ n ] . Additionally, to reduce latency in the calibration process, the uncorrected second derivative of the output y i [ n ] is utilized to replace x i [ n ] , expressed as follows:
y f ^ [ n ] = y [ n ] e f [ n ] e f , 2 [ n ]
with
e f [ n ] = i = 1 < ( M 1 ) / 2 > ( w i [ n ] · y c ^ [ n ] ) + w M / 2 [ n ] · y c ^ [ n ] e x i s t s w h e n M i s e v e n ,
e f , 2 [ n ] = i = 1 < ( M 1 ) / 2 > ( w i , 2 [ n ] · y [ n ] ) + w M / 2 , 2 [ n ] · y [ n ] e x i s t s w h e n M i s e v e n .
Based on the above analysis, the proposed compensation architecture is shown in Figure 4. The outputs of the coarse correction are sent to the fine-correction to eliminate the impact of higher-order error terms. Note that, in the case of a determined number of channels, the part of the error coefficient w i and w i , 2 other than the time-skew errors can be calculated in advance and stored in the circuit, without consuming additional hardware resources.

2.3. Timing Mismatch Estimation

In our previous work [22], the product’s average adjacent channels can be written as follows:
R k , k + 1 = E y k [ n ] · y k + 1 [ n ] = R x T s + γ k + 1 γ k
where R x denotes the autocorrelation function, y k [ n ] denotes the output of k-th channel, and E ( · ) denotes the mean value. The approximation of Equation (26) can be written as
A k = R k , k + 1 R x T s + γ k + 1 γ k · R x T s ,
where R x ( T s ) is the derivative of the autocorrelation of the input signal. To solve the potential stability issues in the feedback architecture [18,20,23,24,25,26], we propose a novel feedforward estimation algorithm to directly calculate the value of timing mismatches.
Firstly, to eliminate R x ( T s ) , the timing-skew error function can be written as
B k = A k + 2 A k = γ k γ k + 1 γ k + 2 + γ k + 3 · R x T s , k = 0 , 1 , , M 3 .
For convenience of expression, we define the γ M = γ 0 . Note that B i is the difference between odd or even terms. To increase the integrity of the error function, we add an additional error function, expressed as follows:
B M 2 = A 2 A 1 = γ 1 2 γ 2 + γ 3 · R x T s .
From Equations (28) and (29), we can obtain the following linear equations:
B 0 = γ 0 γ 1 γ 2 + γ 3 · R x T s B 1 = γ 1 γ 2 γ 3 + γ 4 · R x T s B k = γ k γ k + 1 γ k + 2 + γ k + 3 · R x T s B M 3 = γ M 3 γ M 2 γ M 1 + γ 0 · R x T s B M 2 = γ 1 2 γ 2 + γ 3 · R x T s .
The linear equation system of Equation (30) can be written in matrix form as follows:
C T × γ T = B T · 1 R x T s
where γ T is a column vector and its elements are each sub-ADC’s time-skew error; B T is also a column vector and its elements are each time-skew error function, which can be expressed as:
γ T = γ 0 , γ 1 , , γ M 1 T ,
B T = B 0 , B 1 , , B M 2 T
and
C = 1 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 1 2 1 0 0 ( M 1 ) × M
is a constant circular ( M 1 ) × M matrix. The sum of each row is zero. Note that the rank of C T is M − 1, indicating that we cannot directly find its inverse matrix. In addition, the number of unknown parameters ( γ k , k = 0 , , M 1 ) is higher than the error equations. Therefore, the linear equation system is under-determined and finding the unique minimal norm solution of this system becomes a key challenge.
Although the inverse matrix of C T does not exist, we can use the Moore–Penrose generalized inverse matrix (M–P inverse matrix) to replace it. Firstly, the singular value decomposition of C T can be written as
C T = U S V ,
where U is a ( M 1 ) × ( M 1 ) matrix whose column vectors are left singular vectors; S denotes the diagonal matrix whose elements are singular values; V is a M × M matrix whose column vectors are right singular vectors. U and V are all orthogonal matrices. Hence, the M–P inverse matrix of C T can be written as
C T + = V S 1 U T
where C T + denotes the M–P inverse matrix of C T . The unique minimum-norm solution of the system can be written as
γ T = C T + B T R x T s .
From Ref. [27], the first-order derivative of the autocorrelation of the input signal R x ( T s ) can be approximately computed by the k-th channel output y k [ n ] and the derivative of the ( k + 1 ) -th output y k + 1 [ n ] , expressed as follows:
R x T s E ( y k + 1 [ n ] · y k [ n ] ) = R y k + 1 , y k .
Hence, the elements of the minimum-norm solution of the linear equations are the timing mismatches of each sub-ADC.

2.4. Proposed Calibration Architecture

The flowchart of the proposed algorithm is shown in Figure 5. Figure 6 depicts the proposed timing mismatch calibration architecture for a M-channel TIADC system, which comprises a compensation module and an estimation module. The estimation module encompasses several modules, including the correlation computation module (CCM), error function generation module (EFGM), matrix calculation module (MCM) and down-sampling module (DM). The EFGM comprises multiple subtractors that calculate timing error functions B k . CCM computes the product’s average of adjacent channels R k , k + 1 , which serves as a moving average filter and is composed of various multipliers and adders [22]. The output of R k , k + 1 can be expressed as:
R k , k + 1 [ n ] = N 1 N R k , k + 1 n 1 + 1 N p k [ n ] = 1 N p k [ n ] R k , k + 1 n 1 + R k , k + 1 n 1
where p k [ n ] represents the product of adjacent channels and N denotes the number of samples used in the average calculation. The structure of CCM is described in Figure 7. One of the benefits of utilizing the CCM is that it does not necessitate dedicated memory. Furthermore, N can be set as an integer power of two, enabling the replacement of division with a straightforward shift operation. This approach circumvents the need for a divider. The MCM can perform a matrix multiplication operation to estimate the time skew errors of sub-ADCs. The M–P inverse matrix C T + can be computed in advance and be stored in memory buffers for a given M.

3. Simulation Results and Analyses

To verify and test the performance of the proposed calibration technique, the simulations of a four-channel and an eight-channel TIADC are presented in this section, respectively. We used MATLAB to model our proposed algorithm and acquired non-calibrated data. In order to verify the effectiveness of the algorithm, we also provide many different simulation cases. All the simulations were performed in MATLAB with the optimization of the fixed-point coding and all the data were processed with rounding. We also adopted the ASIC design flow to evaluate the hardware resource cost.

3.1. Simulation of a Four-Channel TIADC

A 14-bit four-channel TIADC behavioral model is introduced in this subsection to evaluate the efficiency of the proposed calibration method. The time-skew errors were set as [0.0013, −0.0008, −0.0007, 0.0001]·Ts. The tap of the derivative FIR filter is 33 and N = 1024.
Figure 8 illustrates the output spectra of a four-channel TIADC prior to and subsequent to calibration using a single-tone signal input at 0.432 · f s . Notably, the spurs caused by timing mismatch are all suppressed effectively, and the SNDR and SFDR improved from 52.82 dB and 56.54 dB to 79.92 dB and 105.98 dB, respectively. The estimated timing mismatch convergence curve corresponding to Figure 6 is shown in Figure 9. Our proposed estimation method needs about 6000 samples to converge at the expected time-skew values.
Figure 10a,b displays the SNDR and SFDR performances with different input sinusoidal frequencies, utilizing the proposed calibration technique. As can be seen, the proposed calibration technique can improve the SNDR and SFDR of TIADC remarkably at almost the entire Nyquist domain and such improvements reach a magnitude of 27 dB for SNDR and 49 dB for SFDR.
The proposed calibration technique performance under different time-skew errors is shown in Figure 11. This demonstrates that our proposed calibration method possesses a stable calibration effect within a range of serious timing mismatches.
Figure 12 illustrates the output spectra of the TIADC with and without calibration when the input signal is a multitone signal. The proposed calibration technique effectively suppresses all spurs caused by timing mismatches and reduces them to the noise floor.
In the above discussion, we assume that both offset and gain mismatches were calibrated before timing mismatch calibration by our proposed technique. However, offset and gain mismatches cannot be completely eliminated in practice [11,28]. To view the effectiveness of our calibration algorithm even in the presence of the three mismatches (i.e., offset, gain and timing mismatches), we set the offset mismatch = [0, 0.0001, −0.0002, 0.0002] and gain mismatch = [1, 1.0001, 1.0001, 0.9998]. The output frequency spectra before and after calibration are presented in Figure 13. It can be seen that our proposed calibration algorithm is able to eliminate the effect of timing-skew errors despite the interference of offset and gain mismatches.
Nevertheless, limited by the bandwidth of the derivative FIR filter, the performance of the proposed calibration algorithm will decline when the input signal is near 1 2 f s . The disadvantage of the feedforward structure is that it has a limited margin-of-error estimate. Figure 11 shows that the performance of the calibration algorithm decreases as the standard deviation of the time-skew error increases. The main reason for this is the reduced precision of the estimation module.

3.2. Simulation of an Eight-Channel TIADC

To demonstrate the extension of the proposed calibration technique for any channel TIADC, the simulations of an eight-channel TIADC are introduced in this subsection. The time skew errors are set as [0.001, 0.002, −0.0015, 0.0013, 0.003, −0.004, −0.003, 0.002] · T s .
Figure 14 illustrates the output spectra of an eight-channel TIADC prior to and subsequent to calibration with a single-tone signal input at 0.432 · f s . The proposed calibration technique results in a significant improvement in both the SNDR and the SFDR. Specifically, the SNDR and SFDR are improved from 43.64 dB and 49.36 dB to 76.39 dB and 90.39 dB, respectively.
Figure 15a,b show the performance of SNDR and SFDR versus different input sinusoidal frequencies. Our proposed calibration technique can also maintain a stable efficiency as the input frequency increases, even for an eight-channel TIADC.
Table 1 illustrates the comparison of the proposed fully-digital calibration technique with the other state-of-the-arts. Compared to Ref. [18], our proposed calibration technique demonstrates no limitation on the channel number of the TIADC and performs effectively under any number of channels. Owing to the limit of Hadamard transform, Ref. [18] only adapts to the TIADC with specific channel numbers. On the contrary, our proposed algorithm is based on the correlation between channels, making it applicable to TIadc with any number of channels. Compared to Refs. [19,20,21], our proposed calibration technique utilizes the conjugate property between spurious signals to reduce the number of estimation parameters, suggesting that this technique requires fewer hardware resources. We constructed the underdetermined equation and solved it using the matrix equation, which makes our calibration technique more compact and efficient. Furthermore, the proposed technique offers substantial advantages in terms of convergence time due to its optimal feedforward architecture.

3.3. ASIC Synthesis

To evaluate the hardware consumption of the proposed calibration structure, the application-specific integrated circuit (ASIC) design flow was adopted in this framework. The proposed calibration structure is implemented using ASIC design flow, targeting a 14-bit 3GS/s eight-channel TIADC. Our proposed calibration technique is optimized with fixed-point coding and implemented in MATLAB. The simulation results obtained from Register Transfer Level (RTL) and MATLAB simulations are consistent. Subsequently, the register transfer level (RTL) design is synthesized to a gate-level netlist with Synopsys design compiler (DC) tool, targeting the 28 nm technology. Logic simulations are carried out by means of the gate-level netlist and Verilog testbench. The obtained Verilog Value-Change Dump (VCD) file provides data on the switching activity of specific signals. By analyzing the VCD file, the power consumption of the proposed calibration structure can be accurately estimated.
The power and area synthesized results for the proposed calibration algorithm are presented in Table 2. The proposed calibration technique exhibits a power consumption of 21.3 mW and occupies a compact area of 0.035 mm2, as demonstrated in the results. Specifically, the coarse-fine correction module utilizing three FIR filters contributes to a substantial 84% of the total power dissipation.

4. Conclusions

In this brief, we propose an all-digital background calibration technique for timing mismatches in TIADC. The basic theory of spurious signals caused by timing mismatches in the frequency domain is illustrated. Based on the above theory, we propose a novel compensation algorithm to eliminate the effect of timing mismatch. Moreover, we utilized the conjugate property between spurious signals to reduce the cost of filter and estimation parameters. A coarse–fine correction architecture was adopted to eliminate higher-order error terms. We also proposed a novel feedforward estimation method to accurately estimate the time-skew errors. We utilized the correlation between adjacent channels to construct an underdetermined equation and solved this using singular value decomposition to obtain time-skew errors. Compared with other feedback architecture, our estimation method can exhibit rapid convergence and is immune to potential stability issues. The proposed calibration technique is applicable to TIADCs with any number of channels, and does not necessitate the use of pilot input signals or supplementary auxiliary ADC channels. The simulation results show the effectiveness of the proposed method in both single-tone and multi-tone input conditions. It also brings about the best improvements in SNFR and SFDR, of more than 27 dB and 49 dB, respectively, for a four-channel TIADC. Finally, the ASIC design flow was adopted to evaluate the hardware cost of the proposed calibration structure.
However, our proposed algorithm is limited by the Nyquist sampling theorem and is not effective for inputs with arbitrary Nyquist bands. Besides, the proposed feedforward estimation structure may result in inaccurate calculations when significant timing mismatches are present. Hence, further research will focus on breaking through the limitations of our calibration on arbitrary input signals through the Nyquist zone by the addition of Hilbert filters. We will also consider the use of a hybrid structure of feedforward and feedback to improve the accuracy of the calibration algorithm while maintaining a fast convergence speed.

Author Contributions

Conceptualization, W.X.; validation, W.X. and Z.Z.; methodology, investigation, and simulation, W.X.; writing, original draft preparation, W.X.; writing, review and editing, W.X., L.L. and Y.D.; funding acquisition, Y.D. All authors have read and agreed to the published version of the manuscript.

Funding

This research was supported in part by the Research Foundation of Strategic Priority Research Program of the Chinese Academy of Sciences (grant number: XDA18030100).

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Yin, G.; Jiren, H.; Zhuang, L.; Yang, L.; He, H. General Architecture of Centralized Unit and Distributed Unit for New Radio. ZTE Commun. 2018, 23–31. [Google Scholar]
  2. Wu, J.; Chou, A.; Yang, C.H.; Ding, Y.; Ko, Y.J.; Lin, S.T.; Liu, W.; Hsiao, C.M.; Hsieh, M.H.; Huang, C.C.; et al. A 5.4 gs/s 12b 500 mw pipeline adc in 28 nm cmos. In Proceedings of the 2013 Symposium on VLSI Circuits, Kyoto, Japan, 12–14 June 2013; pp. C92–C93. [Google Scholar]
  3. Fang, J.; Thirunakkarasu, S.; Yu, X.; Silva-Rivas, F.; Zhang, C.; Singor, F.; Abraham, J. A 5-GS/s 10-b 76-mW time-interleaved SAR ADC in 28 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 2017, 64, 1673–1683. [Google Scholar] [CrossRef]
  4. Kurosawa, N.; Kobayashi, H.; Maruyama, K.; Sugawara, H.; Kobayashi, K. Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 2001, 48, 261–271. [Google Scholar] [CrossRef]
  5. Wang, D.; Zhu, X.; Guo, X.; Luan, J.; Zhou, L.; Wu, D.; Liu, H.; Wu, J.; Liu, X. A 2.6 GS/s 8-Bit time-interleaved SAR ADC in 55 nm CMOS technology. Electronics 2019, 8, 305. [Google Scholar] [CrossRef]
  6. Buchwald, A. High-Speed Time Interleaved ADCs. IEEE Commun. Mag. Artic. News Events Interest Commun. Eng. 2016, 54, 71–77. [Google Scholar] [CrossRef]
  7. Razavi, B. Design Considerations for Interleaved ADCs. IEEE J. Solid-State Circuits 2013, 48, 1806–1817. [Google Scholar] [CrossRef]
  8. Black, W.; Hodges, D. Time interleaved converter arrays. In Proceedings of the Solid-State Circuits Conference Digest of Technical Papers IEEE International, San Francisco, CA, USA, 13–15 February 1980; pp. 14–15. [Google Scholar]
  9. Vogel, C. The impact of combined channel mismatch effects in time-interleaved ADCs. IEEE Trans. Instrum. Meas. 2005, 54, 415–427. [Google Scholar] [CrossRef]
  10. El-Chammas, M.; Murmann, B. General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 2009, 56, 902–910. [Google Scholar] [CrossRef]
  11. Xie, X.; Chen, H.; Yin, Y.; Wang, J.; Li, L.; Deng, H.; Meng, X. All-digital calibration algorithm based on channel multiplexing for TI-ADCs. Microelectron. J. 2022, 126, 105503. [Google Scholar] [CrossRef]
  12. Mafi, H.; Yargholi, M.; Yavari, M. Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs. IEEE Trans. Circuits Syst. Regul. Pap. 2017, 64, 1504–1514. [Google Scholar] [CrossRef]
  13. Niu, H.; Yuan, J. An Efficient Spur-Aliasing-Free Spectral Calibration Technique in Time-Interleaved ADCs. Circuits Syst. Regul. Pap. IEEE Trans. 2020, 67, 2229–2238. [Google Scholar] [CrossRef]
  14. Lu, Z.; Tang, H.; Ren, Z.; Hua, R.; Peng, X. A Timing Mismatch Background Calibration Algorithm with Improved Accuracy. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2021, 29, 1591–1595. [Google Scholar] [CrossRef]
  15. Camarero, D.; Kalaia, K.B.; Naviner, J.F.; Loumeau, P. Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 2008, 55, 3676–3687. [Google Scholar] [CrossRef]
  16. Huang, C.C.; Wang, C.Y.; Wu, J.T. A CMOS 6-Bit 16-GS/s time-interleaved ADC using digital background calibration techniques. IEEE J. Solid-State Circuits 2011, 46, 848–858. [Google Scholar] [CrossRef]
  17. Elbornsson, J.; Gustafsson, F.; Eklund, J.E. Blind equalization of time errors in a time-interleaved ADC system. IEEE Trans. Signal Process. 2005, 53, 1413–1424. [Google Scholar] [CrossRef]
  18. Matsuno, J.; Yamaji, T.; Furuta, M.; Itakura, T. All-digital background calibration technique for time-interleaved ADC using pseudo aliasing signal. IEEE Trans. Circuits Syst. I Regul. Pap. 2013, 60, 1113–1121. [Google Scholar] [CrossRef]
  19. Niu, H.; Yuan, J. A Spectral-Correlation-Based Blind Calibration Method for Time-Interleaved ADCs. Circuits Syst. Regul. Pap. IEEE Trans. 2020, 67, 5007–5017. [Google Scholar] [CrossRef]
  20. Qiu, Y.; Liu, Y.J.; Zhou, J.; Zhang, G.; Chen, D.; Du, N. All-Digital Blind Background Calibration Technique for Any Channel Time-Interleaved ADC. Circuits Syst. Regul. Pap. IEEE Trans. 2018, 65, 2503–2514. [Google Scholar] [CrossRef]
  21. Qiu, Y.; Zhou, J.; Liu, Y.; Zhang, G.; Liu, Y. Novel adaptive blind calibration technique of time-skew mismatches for any channel time-interleaved analogue-to-digital converters. IET Circuits Devices Syst. 2019, 13, 830–835. [Google Scholar] [CrossRef]
  22. Xiong, W.; Zhang, Z.; Sun, L.; Liu, Y.; Liu, H.; Lang, L.; Dong, Y. Fast convergent background calibration technique for timing mismatch in M-channel time-interleaved ADCs. AEU-Int. J. Electron. Commun. 2022, 153, 154282. [Google Scholar] [CrossRef]
  23. Yin, M.; Ye, Z. First order statistic based fast blind calibration of time skews for time-interleaved ADCs. IEEE Trans. Circuits Syst. II Express Briefs 2019, 67, 162–166. [Google Scholar] [CrossRef]
  24. Liu, S.; Zhao, L.; Deng, Z.; Zhang, Z. A digital adaptive calibration method of timing mismatch in TIADC based on adjacent channels Lagrange mean value difference. Circuits Syst. Signal Process. 2021, 40, 6301–6323. [Google Scholar] [CrossRef]
  25. Chen, S.; Wang, L.; Zhang, H.; Murugesu, R.; Dunwell, D.; Carusone, A.C. All-digital calibration of timing mismatch error in time-interleaved analog-to-digital converters. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2017, 25, 2552–2560. [Google Scholar] [CrossRef]
  26. Li, X.; Wu, J.; Vogel, C. A background correlation-based timing skew estimation method for time-interleaved ADCs. IEEE Access 2021, 9, 45730–45739. [Google Scholar] [CrossRef]
  27. Le Duc, H.; Nguyen, D.M.; Jabbour, C.; Desgreys, P.; Jamin, O.; Tam Nguyen, V. Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition. IEEE Trans. Circuits Syst. Regul. Pap. 2017, 64, 1515–1528. [Google Scholar] [CrossRef]
  28. Kang, T.; Zhang, Z.; Xiong, W.; Sun, L.; Liu, Y.; Zhong, W.; Lang, L.; Shan, Y.; Dong, Y. A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm. Electronics 2023, 12, 1319. [Google Scholar] [CrossRef]
Figure 1. (a) The flow chart and (b) the sampling sequence diagram of the M-channel TIADC system.
Figure 1. (a) The flow chart and (b) the sampling sequence diagram of the M-channel TIADC system.
Electronics 12 01965 g001
Figure 2. The block diagram of sampling in an M-channel TIADC.
Figure 2. The block diagram of sampling in an M-channel TIADC.
Electronics 12 01965 g002
Figure 3. (a) The TIADC output spectrum with timing mismatch. (b) The frequency shift in X ( j ω ) . (c) The amplitude modulation of the frequency-shifting parameters. (d) The spectrum of corrected signal Y ^ ( j ω ) .
Figure 3. (a) The TIADC output spectrum with timing mismatch. (b) The frequency shift in X ( j ω ) . (c) The amplitude modulation of the frequency-shifting parameters. (d) The spectrum of corrected signal Y ^ ( j ω ) .
Electronics 12 01965 g003
Figure 4. The structure of the proposed compensation technique. (a) The structure of the coarse correction. (b) The structure of the fine correction.
Figure 4. The structure of the proposed compensation technique. (a) The structure of the coarse correction. (b) The structure of the fine correction.
Electronics 12 01965 g004aElectronics 12 01965 g004b
Figure 5. The flowchart of the proposed algorithm.
Figure 5. The flowchart of the proposed algorithm.
Electronics 12 01965 g005
Figure 6. The structure of the proposed calibration architecture.
Figure 6. The structure of the proposed calibration architecture.
Electronics 12 01965 g006
Figure 7. The structure of CCM.
Figure 7. The structure of CCM.
Electronics 12 01965 g007
Figure 8. Spectra of a four-channel TIADC output for a single tone input at 0.432 · f s . (a) Prior to and (b) subsequent to the proposed digital timing mismatch calibration.
Figure 8. Spectra of a four-channel TIADC output for a single tone input at 0.432 · f s . (a) Prior to and (b) subsequent to the proposed digital timing mismatch calibration.
Electronics 12 01965 g008
Figure 9. Convergences of the estimated timing mismatches.
Figure 9. Convergences of the estimated timing mismatches.
Electronics 12 01965 g009
Figure 10. (a) SNDR and (b) SFDR versus different input frequencies with the adoption of the proposed calibration technique for a four-channel TIADC.
Figure 10. (a) SNDR and (b) SFDR versus different input frequencies with the adoption of the proposed calibration technique for a four-channel TIADC.
Electronics 12 01965 g010
Figure 11. (a) SNDR and (b) SFDR versus different timing-skew mismatches for a four-channel TIADC by utilizing the proposed calibration technique.
Figure 11. (a) SNDR and (b) SFDR versus different timing-skew mismatches for a four-channel TIADC by utilizing the proposed calibration technique.
Electronics 12 01965 g011
Figure 12. Spectra of a four-channel TIADC output (a) without and (b) with calibration under a multitone input.
Figure 12. Spectra of a four-channel TIADC output (a) without and (b) with calibration under a multitone input.
Electronics 12 01965 g012
Figure 13. The frequency spectra of the TIADC output with offset and gain mismatches: (a) before calibration (SFDR = 62.83 dB); (b) after calibration (SFDR = 72.09 dB).
Figure 13. The frequency spectra of the TIADC output with offset and gain mismatches: (a) before calibration (SFDR = 62.83 dB); (b) after calibration (SFDR = 72.09 dB).
Electronics 12 01965 g013
Figure 14. Spectra of an eight-channel TIADC output for a single tone input at 0.432 · f s . (a) Before and (b) after the proposed digital timing mismatch calibration.
Figure 14. Spectra of an eight-channel TIADC output for a single tone input at 0.432 · f s . (a) Before and (b) after the proposed digital timing mismatch calibration.
Electronics 12 01965 g014
Figure 15. (a) SNDR and (b) SFDR versus different input frequencies for an eight-channel TIADC with adoption of proposed calibration technique.
Figure 15. (a) SNDR and (b) SFDR versus different input frequencies for an eight-channel TIADC with adoption of proposed calibration technique.
Electronics 12 01965 g015
Table 1. Comparison of the state-of-the-art calibration methods.
Table 1. Comparison of the state-of-the-art calibration methods.
Characteristics[18][19][20][21]This Work
BackgroundYesYesYesYesYes
Resolution1011-1414
Channels2&8164&164&164&8
Arbitrary channel calibrationNoYesYesYesYes
Matrix operationYesNoNoNoYes
Estimation parameters num.M2M−22M−22M−2M
Convergence time (samples)50 k1200 k60 k20 k6 k
Table 2. The synthesized results of power and area for the proposed calibration algorithm.
Table 2. The synthesized results of power and area for the proposed calibration algorithm.
Module NameArea [µm2]Area %Power [mW]Power [%]
Correction27,34477.217.984
Estimation807622.83.416
Total35,42010021.3100
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Share and Cite

MDPI and ACS Style

Xiong, W.; Zhang, Z.; Lang, L.; Dong, Y. A Novel Fully Digital Feedforward Background Calibration Technique for Timing Mismatch in M-Channel Time-Interleaved ADCs. Electronics 2023, 12, 1965. https://doi.org/10.3390/electronics12091965

AMA Style

Xiong W, Zhang Z, Lang L, Dong Y. A Novel Fully Digital Feedforward Background Calibration Technique for Timing Mismatch in M-Channel Time-Interleaved ADCs. Electronics. 2023; 12(9):1965. https://doi.org/10.3390/electronics12091965

Chicago/Turabian Style

Xiong, Wei, Zhenwei Zhang, Lili Lang, and Yemin Dong. 2023. "A Novel Fully Digital Feedforward Background Calibration Technique for Timing Mismatch in M-Channel Time-Interleaved ADCs" Electronics 12, no. 9: 1965. https://doi.org/10.3390/electronics12091965

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop