Next Article in Journal
Routing Attacks Detection in 6LoWPAN-Based Internet of Things
Next Article in Special Issue
A Novel Fully Digital Feedforward Background Calibration Technique for Timing Mismatch in M-Channel Time-Interleaved ADCs
Previous Article in Journal
A Novel Source Code Clone Detection Method Based on Dual-GCN and IVHFS
Previous Article in Special Issue
Cooperative Localization of Firefighters Based on Relative Ranging Constraints of UWB and Autonomous Navigation
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm

1
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
2
Microelectronic Equipment Technology Department, University of Chinese Academy of Sciences, Beijing 100049, China
3
Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
*
Author to whom correspondence should be addressed.
Electronics 2023, 12(6), 1319; https://doi.org/10.3390/electronics12061319
Submission received: 9 February 2023 / Revised: 5 March 2023 / Accepted: 8 March 2023 / Published: 9 March 2023
(This article belongs to the Special Issue Advanced Technologies in Digital Signal Processing)

Abstract

:
Timing-mismatch errors among channels in time-interleaved analog-to-digital converters (TIADCs) greatly degrade the whole performance of the system. Therefore, techniques for calibrating timing mismatch are indispensable, and a new fully-digital calibration technique is presented in this article. Based on a Hilbert filter, modified moving averagers (MMAs) and inverse cosine functions, the proposed estimation algorithm is fast (within 1200 sample points) and accurate. Meanwhile, the coordinate rotational digital computer (CORDIC) algorithm, which is used to implement inverse cosine functions, is also improved, giving it higher precision. In addition, a compensation method based on second-order Taylor series approximation with less hardware resource consumption is provided. Through analyses and simulations, this calibration technique proved to be suitable for TIADCs with an arbitrary number of channels, in which the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were, respectively, improved from 24.06 dB and 24.57 dB to 67.96 dB and 85.69 dB.

1. Introduction

In modern analog–digital hybrid signal processing systems, high-speed and high-resolution analog-to-digital converters (ADCs) are one of the core components that are used to achieve their high performance [1,2]. However, a single ADC can no longer meet the indicators that are constricted by integrated circuit technology [3]. With multiple channels, TIADCs can increase the sampling rate while maintaining the resolution in ideal conditions, and they have become an optimal choice for improving the overall performance of systems.
A TIADC consists of M ADCs sampling in parallel and the sampled signals are output alternately, as shown in the block diagram in Figure 1. Due to the influence of the fabrication process and environmental factors such as temperature, voltage and aging [4], ADCs in different channels cannot have the same device characteristics. This leads to mismatch errors among channels, including offset, gain, bandwidth and timing errors. All of these mismatch errors have a great impact on the dynamic performance of a TIADC, affecting factors such as the SNDR and the SFDR. The timing mismatch, as the most influential factor [5,6,7,8,9], requires more sophisticated calibration methods because of the input’s frequency dependence and nonlinearity. Since the TIADC architecture was proposed in 1980 [10], calibration techniques of timing mismatch, including estimation algorithms and compensation methods, have been the focus of attention. Therefore, calibrating timing mismatch quickly and accurately is a key problem and will be discussed in this article.
The calibration techniques of TIADCs can be generally divided into foreground and the background techniques. The former are simple in structure and easy to implement, but they require a reference signal or they will interrupt the sampling operation in order to complete the calibration. The latter can calibrate and adjust during TIADC work, but they have the disadvantages of being highly complex and having high resource consumption. In practice, the choice should be flexible according to different scenarios.
As for estimation algorithms, one effective approach is blind estimation [11,12,13,14,15]. In [11], two of the channels were regarded as the reference channels, and the mismatch value could then be obtained by a series of calculations and the least mean square (LMS) algorithm. Blind estimation techniques are flexible to use, but the convergence speed and nonuniform sampling become the main problems. Another option is based on signal correlation [16,17,18,19,20]. The method in [16] estimated the timing mismatch through the difference in the autocorrelation functions between adjacent channels. In [17], the cross-correlation was measured between nonconsecutive channels. In this way, the number of channels must be a power of two, and the calibration process is performed over several stages. In addition, the sine-wave fitting method is also practicable [21,22]. In [22], the timing mismatch was estimated at one instance using a Hilbert transform and an inverse tangent function. Although this algorithm could converge fast with low complexity, the calibration result was poor for the high-frequency input signal case.
With regard to compensation in the digital domain, there are methods that are based on fractional delay filters [23,24,25], Taylor approximation [19,26,27,28,29] and so on. Law, Hurst and Lewis [24] used all-pass fractional delay filter banks to compensate for the timing mismatch. However, in order to eliminate the ripple effects caused by the Gibbs phenomenon [30], the filter coefficients were usually windowed, which made this a nonoptimal solution. In [26,27], a first-order Taylor series expansion was used for the approximation, and timing mismatch was then compensated for through multi-phase finite impulse response (FIR) filters. This method has the advantages of high computational efficiency and fast calibration. However, each filter needs a set of adders and multipliers, and the resource overhead increases linearly with the increasing number of channels. Moreover, compensation means in the analog domain are also feasible. The work of [31] employed digital-to-analog converters (DACs) and delay lines to compensate, nonetheless, the accuracy of this was obviously affected by the operating environment of the devices.
In this article, a novel fully-digital timing-mismatch calibration technique for TIADCs of any number of channels is proposed. As for the estimation algorithm, a Hilbert filter, MMAs and inverse cosine functions were used. Compared to the means in [22], this algorithm used inverse cosine functions rather than inverse tangent functions, in which the influence of symbols could be avoided in the operation result. Therefore, our proposed estimation was faster and its consequences did not deteriorate with increasing input frequency. Meanwhile, we provided a solution for hardware implementation of inverse cosine functions through an improved CORDIC algorithm, and, thus, these functions could be calculated with extreme precision. On the other hand, the compensation method was based on second-order Taylor series approximation, which reduced hardware resource consumption significantly without any derivative filters.
The remainder of this article is organized as follows. Section 2 presents the proposed timing-mismatch calibration technique. Results and analyses are provided in Section 3. Finally, Section 4 concludes this article.

2. Proposed Calibration Technique

2.1. TIADC Mathematical Model

To facilitate discussions of the timing mismatch theoretically, the mathematical model of TIADC is provided. For an ideal M-channel TIADC that takes sine wave signals as input, we can assume that the output of the ith channel is as follows:
x i , i d e a l [ n ] = s i n ( 2 π f i n · ( n M + i ) · T s ) ,
where f i n is the input signal frequency, T s denotes the TIADC sampling period and i = 0 , 1 , , M 1 . If timing mismatch is considered, the output of the ith channel can be expressed as follows:
x i [ n ] = s i n ( 2 π f i n · ( ( n M + i ) · T s + τ i ) ) ,
where τ i indicates the timing mismatch of the ADC in the ith channel. The sampling sequence diagram of the M-channel TIADC system with τ i is shown in Figure 2.
Before dealing with timing mismatch, other mismatches need to be calibrated completely. Hence, offset, gain and bandwidth mismatches are neglected here.

2.2. Timing-Mismatch Estimation

In this subsection, an estimation algorithm based on a Hilbert filter, MMAs and inverse cosine functions is introduced. According to Equation (2), we can apply Hilbert transforms to the output of M ADCs, and the complex signal of the ith channel is as follows:
x i h [ n ] = c o s ( 2 π f i n · ( ( n M + i ) · T s + τ i ) ) .
We can then multiply the outputs between adjacent channels and assign the result to A j :
A j = x j [ n ] · x j + 1 [ n ] = s i n ( 2 π f i n · ( ( n M + j ) · T s + τ j ) ) · s i n ( 2 π f i n · ( ( n M + j + 1 ) · T s + τ j + 1 ) ) = s i n ( α ) · s i n ( β ) ,
where α and β separately denote 2 π f i n · ( ( n M + j ) · T s + τ j ) and 2 π f i n · ( ( n M + j + 1 ) · T s + τ j + 1 ) , and j = 0 , 1 , , M 2 . Meanwhile, the same operation is applied to the complex signals through a Hilbert transform and the product B j is as follows:
B j = x j h [ n ] · x j + 1 h [ n ] = c o s ( 2 π f i n · ( ( n M + j ) · T s + τ j ) ) · c o s ( 2 π f i n · ( ( n M + j + 1 ) · T s + τ j + 1 ) ) = c o s ( α ) · c o s ( β ) .
After multiplications, we obtain C j by summing over A j and B j :
C j = A j + B j = s i n ( α ) · s i n ( β ) + c o s ( α ) · c o s ( β ) = c o s ( β α ) = c o s ( 2 π f i n · ( T s + τ j + 1 τ j ) ) .
In order to eliminate statistical errors and noise interference, we perform an MMA on C j and obtain the averaged output D j as follows:
D j = 1 N · C j [ n ] + N 1 N · C j ¯ [ n 1 ] c o s ( 2 π f i n · ( T s + τ j + 1 τ j ) ) ,
where N is the sample number of the MMA and C j ¯ [ n 1 ] indicates the average value from C j [ n 1 ] to C j [ n N + 1 ] . The inverse cosine function is then implemented by a CORDIC algorithm and the result E j is as follows:
E j = a r c c o s ( D j ) = 2 π f i n · ( T s + τ j + 1 τ j ) .
After that, the difference of timing mismatches between adjacent channels, F j , can be easily obtained:
F j = τ j + 1 τ j = E j 2 π f i n T s .
Obviously, there are M mismatch values to be solved and M 1 equations in Equation (9). Moreover, only the relative difference of timing mismatches among channels is focused on, that is, we can assume the following:
i = 0 M 1 τ i = 0 .
The value of all timing mismatches can now be calculated by solving the system in Equations (9) and (10). If we define τ = [ τ 0 , τ 1 , , τ M 1 ] T and F = [ F 0 , F 1 , , F M 2 , 0 ] T , a matrix equation can be described as follows:
C · τ = F ,
where C is the coefficient matrix of full rank and its inverse matrix C 1 always exists. Hence, the vector τ can be obtained as follows:
τ = C 1 · F .
If M = 4 , we have
C 1 = 1 4 3 2 1 0 1 2 1 0 1 2 1 0 1 2 3 0 .
The overall block diagram of the proposed calibration technique is presented in Figure 3, and Figure 4 is the implementation structure of the estimation algorithm. The inverse cosine function is implemented by an improved CORDIC algorithm, which is introduced in next subsection.

2.3. The Improved CORDIC Algorithm

Traditional ways to implement an inverse cosine function include the table look-up scheme and polynomial approximation, both of which take up a number of resources and do not obtain accurate calculation results. The CORDIC algorithm, in contrast, can enhance computational accuracy with less hardware resource consumption.
Using only shift and addition operations, the CORDIC algorithm keeps rotating at a small angle on a unit circle to approximate the desired angle [32]. The iterative formula for calculating the value of an inverse cosine is as follows:
x k + 1 = x k s k · y k · 2 k y k + 1 = y k + s k · x k · 2 k z k + 1 = z k + s k · a r c t a n ( 2 k ) ,
where k indicates the kth iteration, x k is the abscissa value, y k is the ordinate value, z k is therotation angle and s k controls the rotation direction by judging the sign:
s k = s i g n ( x k D j ) ,
where D j is the cosine value being solved in Figure 3. After m iterations, the result is
x m = D j y m = ( L m y 0 ) 2 + D j 2 z m = z 0 + a r c c o s ( D j L m 1 x 0 1 ) ,
where L m is the scale factor and L m 1.64676 for radix-2 CORDIC. According to Equation (16), we set x 0 = L m 1 0.60725 , y 0 = 0 and z 0 = 0 , and the value of the inverse cosine E j can then be obtained.
Nevertheless, some aspects of the CORDIC algorithm still need improvement, such as the range limit of the rotation angle and defective pixels when calculating an inverse cosine.
Firstly, the rotation angle θ k = a r c t a n ( 2 k ) is limited by the number of iterations m:
k = 0 m 1 a r c t a n ( 2 k ) θ k = 0 m 1 a r c t a n ( 2 k ) .
When m , the range of θ is [ 99.827 , 99.827 ] . However, the angle of the cosine function is in [ 0 , π ] . Thus, the quadrant should be transformed as follows by the cosine function relations, as shown in Figure 5a:
c o s θ = c o s ( π θ ) = c o s ( π + θ ) = c o s ( θ )
Secondly, the rotation direction, s k , is affected and generates defective pixels. As the initial value x 0 0.60725 1 , this means the initial point is not on the unit circle, as shown in Figure 5b. Therefore, s k needs to be modified before applying the CORDIC algorithm:
s k = 1 ,   D j m a x { x k , c o s ( z k ) } 1 ,   e l s e
The block diagram of the improved CORDIC algorithm is presented in Figure 6, and the improvement effect is shown in Section 3.

2.4. Timing-Mismatch Compensation

With the estimated value of timing mismatch, τ i , any compensation method is feasible theoretically. Here, we propose a new method based on second-order Taylor series approximation, which is optimized according to the estimation algorithm so as to reduce hardware resource consumption.
From the perspective of the frequency domain, the existence of timing mismatch is equivalent to multiplying the ideal signal x i , i d e a l [ n ] by a factor of e j ω τ i [27]. Therefore, we can eliminate the effect of τ i through multiplying by a factor of e j ω τ i , whose second-order Taylor approximation is as follows:
e j ω τ i 1 j ω τ i + 1 2 · ( j ω ) 2 · τ i 2 .
Based on the analysis above, the output signals can be compensated for in the time domain as follows:
x ^ i [ n ] x i [ n ] τ i · x i [ n ] + 1 2 τ i 2 · x i [ n ] ,
where x ^ i [ n ] denotes the compensated signal, and x i [ n ] and x i [ n ] , respectively, indicate the first and second derivative of x i [ n ] , which can be expressed as follows:
x i [ n ] = 2 π f i n · c o s ( 2 π f i n · ( ( n M + i ) · T s + τ i ) ) = 2 π f i n · x i h [ n ]
x i [ n ] = ( 2 π f i n ) 2 · s i n ( 2 π f i n · ( ( n M + i ) · T s + τ i ) ) = ( 2 π f i n ) 2 · x i [ n ] .
By exploiting the Hilbert filter, the use of derivative filters can be circumvented. Finally, we substitute Equations (22) and (23) into Equation (21), and x ^ i [ n ] becomes the following:
x ^ i [ n ] x i [ n ] 2 π f i n τ i · x i h [ n ] 2 · ( π f i n τ i ) 2 · x i [ n ] .
Equation (24) is the key idea of the proposed compensation method, and its implementation structure is shown in Figure 7.

3. Results and Analyses

3.1. Simulation Results

In this subsection, the simulation of the proposed calibration technique on a four-channel TIADC using MATLAB (R2022a, Win64) is described. In order to verify the calibration effectiveness, we set the timing mismatches τ = [ 0.031 , 0.015 , 0.013 , 0.027 ] · T s and the resolution of the TIADC was 12 bits.

3.1.1. Improved CORDIC Algorithm

For the purpose of testing the performance of the improved CORDIC algorithm, it was compared with the inverse cosine function in MATLAB and the traditional CORDIC algorithm without any improvements. The iteration number of the CORDIC algorithm was set to 20 and the comparison results are shown in Figure 8 and Figure 9.
Figure 8 shows the curve of the inverse cosine, from which we can easily find the severe deviations of the inverse cosine function from the traditional CORDIC algorithm and MATLAB at cosine values of ±0.6074, ±0.9114 and ±0.9963. For further observation, 20,000 points were sampled uniformly in the domain [ 1 , 1 ] in order to test the relative errors of the CORDIC algorithm with and without improvement, as exhibited in Figure 9. Obviously, the relative errors of the traditional CORDIC algorithm were very large and the maximum one was about 0.26, resulting in a decline of estimation accuracy. Conversely, the relative errors of the improved CORDIC algorithm were within 5 × 10 6 and, thus, the accuracy was unaffected. Therefore, the improvement is fairly effective and the proposed CORDIC algorithm can be applied perfectly.

3.1.2. Estimation Speed

One of the advantages of the proposed estimation algorithm is its fast calculation speed. Owing to our estimation being free from a feedback system, its speed depends heavily on the MMA sample number N. For hardware implementation, N is usually taken to be a power of 2 and we observed that the best value was 128 through experiments. The simulation result of the calculation speed is shown in Figure 10, it indicates that the estimated values became stable within 1200 sample points.

3.1.3. Calibration Results

With an input of f i n = 0.437 · f s , the TIADC output frequency spectra before and after calibration are shown in Figure 11. It can be seen that the proposed calibration technique effectively suppressed the spurs induced by timing mismatches. The SNDR was increased from 24.06 dB to 67.96 dB, and the SFDR was increased from 24.57 dB to 85.69 dB. The effective number of bits (ENOB) was calculated as 11.00 by Equation (25) [33]:
E N O B = S N D R 1.76 6.02 .
To verify the calibration effect with different input frequencies, 480 sample points were set uniformly when f i n / f s was in [ 0.01 , 0.49 ] . Meanwhile, first-order, second-order and third-order Taylor series approximation were applied to compensate, and the comparison result is shown in Figure 12. Obviously, the compensation effect of first-order Taylor series approximation was poorer and the other two had similar effects. So, second-order Taylor series approximation was chosen over third-order Taylor series approximation due to its lower hardware resource consumption. The performance of the SNDR and the SFDR were remarkably improved and were often immune to the change in input frequency. After calibration, the SNDR (SFDR) was stable at 68 (83) dB, and its overall improvement was as high as 8∼46 (22∼61) dB.

3.1.4. Robustness Testing

In practice, offset and gain mismatches cannot be completely eliminated. To test the robustness of the proposed timing-mismatch calibration method, the other two mismatches were set as o f f   s e t   =   [ 0.002 , 0.003 , 0 , 0.001 ] and g a i n   = [ 1.001 , 1 , 0.999 , 1.001 ] , and the TIADC output frequency spectra before and after calibration are presented in Figure 13. As can be seen, the timing mismatch was significantly reduced after calibration, and the other two mismatches became the main errors.
In order to further verify the robustness of this calibration technique, some white noise was applied to the timing mismatch to simulate the changes in the application environment. This white noise was set randomly in the range [ 0.01 ,   0.01 ] · T s at 5000, 10,000 and 15,000 sample points. As shown in Figure 14, the changes originating from the white noise could be tracked by the estimation algorithm within 500 sample points. At the same time, the compensation effect remained unchanged, meaning that the proposed method could withstand some environmental changes.

3.2. ASIC Synthesis

To calculate the hardware consumption of the proposed calibration technique, the application-specific integrated circuit (ASIC) design flow was adopted in this work. After fixed-point coding, the register transfer level (RTL) design was compiled and verified through a Verilog compiled simulator (VCS). It was then synthesized to a gate-level netlist using the Synopsys design compiler (DC) tool, targeting the 28 nm technology. The synthesized results of area and power at an input frequency of 0.437 · f s are shown in Table 1. It could be seen that the total area was 20,784 μ m 2 and the total power was 10.5 mW. The estimation algorithm, as the main part of the calibration technique, accounted for 42.2% of the total area and 41% of the total power. The compensation method consumed 4391 μ m 2 and its power was only 2.5 mW.

3.3. Performance Comparison

Table 2 shows the comparison of the proposed fully-digital timing-mismatch calibration technique with the other three works that have been reported in recent years [18,22,27]. With the same number of channels and similar resolution, the timing-mismatch setting of this work was maximized and the highest input signal frequency was used. As for the estimation speed, the proposed method was much faster than its counterparts. Moreover, the calibration performance in [22] degraded when using high-frequency signal input, which was absence of our work thanks to the inverse cosine functions and the improved CORDIC algorithm. In addition, the proposed calibration technique consumed less hardware resources compared with the other three techniques.

4. Conclusions

In this article, a novel fully-digital timing-mismatch calibration technique is formulated for TIADCs with an arbitrary number of channels. A new method based on a Hilbert filter, MMAs and inverse cosine functions is proposed for estimation. This method possesses both low hardware complexity and fast calculation speed, thus, it is quite suitable for the systems that carry low power and stable input signals. An improved CORDIC algorithm is presented to provide a feasible hardware implementation for inverse cosine functions. Moreover, a new compensation method based on second-order Taylor series approximation is offered. By reusing the output of the Hilbert filter, hardware resource consumption was reduced. At last, the calibration performance and the robustness were verified by simulations, and the results of ASIC synthesis and performance comparison were provided.

Author Contributions

Conceptualization, T.K. and Y.D.; methodology, T.K.; software, T.K. and W.Z.; validation, T.K., W.X. and L.S.; formal analysis, T.K. and Y.L.; resources, T.K. and Y.S.; data curation, L.S. and Y.L.; writing—original draft preparation, T.K.; writing—review and editing, T.K., Z.Z., W.X., L.S., Y.L. and L.L.; visualization, T.K.; supervision, Z.Z., Y.S. and Y.D.; project administration, L.L., Y.S. and Y.D.; funding acquisition, Y.S. and Y.D. All authors have read and agreed to the published version of the manuscript.

Funding

This research was supported in part by the Research Foundation of Strategic Priority Research Program of the Chinese Academy of Sciences (grant number: XDA18030100).

Data Availability Statement

Not applicable.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Jia, H.; Guo, X.; Wu, D.; Zhou, L.; Luan, J.; Wu, N.; Huang, Y.; Zheng, X.; Wu, J.; Liu, X. A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration. Electronics 2020, 9, 910. [Google Scholar] [CrossRef]
  2. Huang, W.; Wang, H.; Ye, P.; Yang, K.; Jiang, J.; Pan, H. Novel sifting-based solution for multiple-converter synchronization of ultra-fast TIADC systems. IEICE Electron. Express 2015, 12, 20150585. [Google Scholar] [CrossRef] [Green Version]
  3. Khakpour, A.; Karimian, G. A New Fast Convergent Blind Timing Skew Error Correction Structure for TIADC. IEEE Trans. Circuits Syst. II Express Briefs 2020, 68, 1512–1516. [Google Scholar] [CrossRef]
  4. Kurosawa, N.; Kobayashi, H.; Maruyama, K.; Sugawara, H.; Kobayashi, K. Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 2001, 48, 261–271. [Google Scholar] [CrossRef] [Green Version]
  5. Razavi, B. Design considerations for interleaved ADCs. IEEE J. Solid-State Circuits 2013, 48, 1806–1817. [Google Scholar] [CrossRef] [Green Version]
  6. Yang, K.; Shi, J.; Tian, S.; Huang, W.; Ye, P. Timing skew calibration method for TIADC-based 20 GSPS digital storage oscilloscope. J. Circuits Syst. Comput. 2016, 25, 1650007. [Google Scholar] [CrossRef]
  7. Chen, H.; Pan, Y.; Yin, Y.; Lin, F. All-digital background calibration technique for timing mismatch of time-interleaved ADCs. Integration 2017, 57, 45–51. [Google Scholar] [CrossRef]
  8. Liu, S.; Zhao, L.; Deng, Z.; Zhang, Z. A digital adaptive calibration method of timing mismatch in TIADC based on adjacent channels Lagrange mean value difference. Circuits Syst. Signal Process. 2021, 40, 6301–6323. [Google Scholar] [CrossRef]
  9. Ta, V.T.; Hoang, V.P.; Pham, V.P.; Pham, C.K. An improved all-digital background calibration technique for channel mismatches in high speed time-interleaved analog-to-digital converters. Electronics 2020, 9, 73. [Google Scholar] [CrossRef] [Green Version]
  10. Black, W.C.; Hodges, D.A. Time interleaved converter arrays. IEEE J. Solid-State Circuits 1980, 15, 1022–1029. [Google Scholar] [CrossRef]
  11. Chen, S.; Wang, L.; Zhang, H.; Murugesu, R.; Dunwell, D.; Carusone, A.C. All-digital calibration of timing mismatch error in time-interleaved analog-to-digital converters. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2017, 25, 2552–2560. [Google Scholar] [CrossRef]
  12. Le Duc, H.; Hoang, V.P.; Nguyen, D.M.; Pham, C.K. Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands. In Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018; pp. 1–4. [Google Scholar]
  13. Liu, X.; Xu, H.; Liu, H.; Wang, Y. An efficient blind calibration method for nonlinearity mis-matches in M-channel TIADCs. IEICE Electron. Express 2017, 14, 20170468. [Google Scholar] [CrossRef]
  14. Khakpour, A.; Karimian, G. An Oversampling-Based Fast Convergent Blind Technique for Gain Mismatch and Timing Skew Error Correction in Time-Interleaved ADCs. Circuits Syst. Signal Process. 2022, 102, 1–17. [Google Scholar] [CrossRef]
  15. Bai, X.; Hu, H.; Li, W.; Liu, F. Blind calibration method for two-channel time-interleaved analog-to-digital converters based on FFT. J. Electron. Test. 2018, 34, 643–650. [Google Scholar] [CrossRef]
  16. Salib, A.; Flanagan, M.F.; Cardiff, B. A high-precision time skew estimation and correction technique for time-interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 2019, 66, 3747–3760. [Google Scholar] [CrossRef] [Green Version]
  17. Uran, A.; Kilic, M.; Leblebici, Y. Generalization of referenceless timing mismatch calibration methods for time-interleaved ADCs. In Proceedings of the 2018 14th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), Prague, Czech Republic, 2–5 July 2018; pp. 21–24. [Google Scholar]
  18. Lu, Z.; Tang, H.; Ren, Z.; Hua, R.; Zhuang, H.; Peng, X. A Timing Mismatch Background Calibration Algorithm With Improved Accuracy. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2021, 29, 1591–1595. [Google Scholar] [CrossRef]
  19. Xiong, W.; Zhang, Z.; Sun, L.; Liu, Y.; Liu, H.; Lang, L.; Dong, Y. Fast convergent background calibration technique for timing mismatch in M-channel time-interleaved ADCs. AEU-Int. J. Electron. Commun. 2022, 153, 154282. [Google Scholar] [CrossRef]
  20. Gu, Y.; Feng, X.; Chi, R.; Wu, J.; Chen, Y. A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology. Electronics 2022, 11, 3198. [Google Scholar] [CrossRef]
  21. Park, Y.; Kim, J.; Kim, C. A scalable bandwidth mismatch calibration technique for time-interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 2016, 63, 1889–1897. [Google Scholar] [CrossRef]
  22. Li, X.; Zhi, H.; Ding, D.; Wu, J. An Efficient All-Digital Timing Skew Estimation Method for Time-Interleaved ADCs. In Proceedings of the 2021 IEEE 4th International Conference on Electronics Technology (ICET), Chengdu, China, 7–10 May 2021; pp. 269–273. [Google Scholar]
  23. Huang, S.; Levy, B.C. Blind calibration of timing offsets for four-channel time-interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 2007, 54, 863–876. [Google Scholar] [CrossRef]
  24. Law, C.H.; Hurst, P.J.; Lewis, S.H. A four-channel time-interleaved ADC with digital calibration of interchannel timing and memory errors. IEEE J. Solid-State Circuits 2010, 45, 2091–2103. [Google Scholar] [CrossRef]
  25. De Teyou, G.K.; Petit, H.; Loumeau, P. Adaptive and digital blind calibration of transfer function mismatch in time-interleaved ADCs. In Proceedings of the 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), Grenoble, France, 7–10 June 2015; pp. 1–4. [Google Scholar]
  26. Lin, C.Y.; Wei, Y.H.; Lee, T.C. A 10-bit 2.6-GS/s time-interleaved SAR ADC with a digital-mixing timing-skew calibration technique. IEEE J. Solid-State Circuits 2018, 53, 1508–1517. [Google Scholar] [CrossRef]
  27. Yin, M.; Ye, Z. First order statistic based fast blind calibration of time skews for time-interleaved ADCs. IEEE Trans. Circuits Syst. II Express Briefs 2019, 67, 162–166. [Google Scholar] [CrossRef]
  28. Xie, X.; Chen, H.; Yin, Y.; Wang, J.; Li, L.; Deng, H.; Meng, X. All-digital calibration algorithm based on channel multiplexing for TI-ADCs. Microelectron. J. 2022, 126, 105503. [Google Scholar] [CrossRef]
  29. Yin, Y.; Sun, K.; Chen, H.; Wang, X.; Liu, L.; Deng, H.; Meng, X.; Li, K.; Wang, Z. Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data. IEICE Electron. Express 2020, 17, 20190699. [Google Scholar] [CrossRef] [Green Version]
  30. Mitra, S.K.; Kuo, Y. Digital Signal Processing: A Computer-Based Approach; McGraw-Hill: New York, USA, 2011; Volume 1221. [Google Scholar]
  31. Cao, Y.; Miao, P.; Li, F.; Wang, H. An efficient background timing skew calibration technique for time-interleaving analog-to-digital converters. IEICE Electron. Express 2019, 16, 20190352. [Google Scholar] [CrossRef]
  32. Saravanan, P.; Ramasamy, S. Sine/cos generator for direct digital frequency synthesizer using pipelined CORDIC processor. In Proceedings of the 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT), Tiruchengode, India, 4–6 July 2013; pp. 1–6. [Google Scholar]
  33. Maloberti, F. Data Converters; Springer Science & Business Media: Berlin/Heidelberg, Germany, 2007. [Google Scholar]
Figure 1. A block diagram of an M-channel TIADC.
Figure 1. A block diagram of an M-channel TIADC.
Electronics 12 01319 g001
Figure 2. The sampling sequence diagram of an M-channel TIADC with timing mismatch τ i .
Figure 2. The sampling sequence diagram of an M-channel TIADC with timing mismatch τ i .
Electronics 12 01319 g002
Figure 3. The overall block diagram of the proposed timing-mismatch calibration technique.
Figure 3. The overall block diagram of the proposed timing-mismatch calibration technique.
Electronics 12 01319 g003
Figure 4. The implementation structure of the proposed timing-mismatch estimation algorithm based on a Hilbert filter, MMAs and inverse cosine functions.
Figure 4. The implementation structure of the proposed timing-mismatch estimation algorithm based on a Hilbert filter, MMAs and inverse cosine functions.
Electronics 12 01319 g004
Figure 5. The improvement of the CORDIC algorithm: (a) quadrant transform; (b) parameter modification.
Figure 5. The improvement of the CORDIC algorithm: (a) quadrant transform; (b) parameter modification.
Electronics 12 01319 g005
Figure 6. The block diagram of the improved CORDIC algorithm.
Figure 6. The block diagram of the improved CORDIC algorithm.
Electronics 12 01319 g006
Figure 7. The implementation structure of the proposed timing-mismatch compensation method based on second-order Taylor series approximation.
Figure 7. The implementation structure of the proposed timing-mismatch compensation method based on second-order Taylor series approximation.
Electronics 12 01319 g007
Figure 8. The inverse cosine curve with and without improvement.
Figure 8. The inverse cosine curve with and without improvement.
Electronics 12 01319 g008
Figure 9. The relative errors with and without improvement.
Figure 9. The relative errors with and without improvement.
Electronics 12 01319 g009
Figure 10. The calculation speed of the proposed estimation algorithm when the MMA sample number N = 128 .
Figure 10. The calculation speed of the proposed estimation algorithm when the MMA sample number N = 128 .
Electronics 12 01319 g010
Figure 11. The frequency spectra of the TIADC output when f i n / f s = 0.437 : (a) before calibration (SNDR = 24.04 dB, SFDR = 24.57 dB); (b) after calibration (SNDR = 67.96 dB, SFDR = 85.69 dB).
Figure 11. The frequency spectra of the TIADC output when f i n / f s = 0.437 : (a) before calibration (SNDR = 24.04 dB, SFDR = 24.57 dB); (b) after calibration (SNDR = 67.96 dB, SFDR = 85.69 dB).
Electronics 12 01319 g011
Figure 12. The results of the proposed calibration method versus different input frequencies: (a) SNDR; (b) SFDR.
Figure 12. The results of the proposed calibration method versus different input frequencies: (a) SNDR; (b) SFDR.
Electronics 12 01319 g012
Figure 13. The frequency spectra of the TIADC output with offset and gain mismatches when f i n / f s = 0.437 : (a) before calibration (SNDR = 24.04 dB, SFDR = 24.57 dB); (b) after calibration (SNDR = 50.28 dB, SFDR = 53.04 dB).
Figure 13. The frequency spectra of the TIADC output with offset and gain mismatches when f i n / f s = 0.437 : (a) before calibration (SNDR = 24.04 dB, SFDR = 24.57 dB); (b) after calibration (SNDR = 50.28 dB, SFDR = 53.04 dB).
Electronics 12 01319 g013
Figure 14. The calculation speed of the proposed estimation algorithm with random white noise at 5000, 10,000 and 15,000 sample points.
Figure 14. The calculation speed of the proposed estimation algorithm with random white noise at 5000, 10,000 and 15,000 sample points.
Electronics 12 01319 g014
Table 1. The synthesized results of power and area.
Table 1. The synthesized results of power and area.
ModuleArea ( μ m 2 )Area %Power (mW)Power %
Estimation876842.24.341
Compensation439121.12.523.8
Hilbert filters762536.73.735.2
Total20,78410010.5100
Table 2. The performance comparison results.
Table 2. The performance comparison results.
CharacteristicsRef. [18]Ref. [22]Ref. [27]This Work
Channel number4444
Resolution (bit)12101212
Timing mismatch ( · T s ) *0.030.0250.0240.031
Input frequency ( · f s )0.4200.3470.1500.437
Estimation speed (samples)204.8 K16 K3.1 K1.2 K
SNDR (dB)64.361.969.267.96
SFDR (dB)86.985.876.485.69
ENOB (bit)10.399.9911.2011.00
* Only the maximum timing-mismatch values are shown here.
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Share and Cite

MDPI and ACS Style

Kang, T.; Zhang, Z.; Xiong, W.; Sun, L.; Liu, Y.; Zhong, W.; Lang, L.; Shan, Y.; Dong, Y. A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm. Electronics 2023, 12, 1319. https://doi.org/10.3390/electronics12061319

AMA Style

Kang T, Zhang Z, Xiong W, Sun L, Liu Y, Zhong W, Lang L, Shan Y, Dong Y. A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm. Electronics. 2023; 12(6):1319. https://doi.org/10.3390/electronics12061319

Chicago/Turabian Style

Kang, Tong, Zhenwei Zhang, Wei Xiong, Lin Sun, Yu Liu, Wei Zhong, Lili Lang, Yi Shan, and Yemin Dong. 2023. "A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm" Electronics 12, no. 6: 1319. https://doi.org/10.3390/electronics12061319

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop