Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application

Abstract

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.

1. Introduction

Spin-transfer torque magnetic random-access memory (STT-MRAM) has garnered significant interest as an excellent prospect for on-chip cache memory applications, owing to its advantageous attributes, such as high integration density, low leakage power consumption, inherent nonvolatility, and compatibility with the complementary metal–oxide–semiconductor (CMOS) fabrication process [1,2,3,4,5,6,7,8,9,10].

A standard configuration of an STT-MRAM cell involves a single access transistor accompanied by a magnetic tunnel junction (MTJ) that serves as a storage element. Within this MTJ structure lies a pinned layer (PL) and a free layer (FL), sandwiching a tunneling oxide barrier, as depicted in Figure 1a. The magnetization of the PL is anchored in one direction, whereas that of the FL can be manipulated by passing an electrical current. The FL magnetization conventionally rests in two distinct states: parallel (P) or antiparallel (AP) with respect to the PL orientation. The antiparallel state results in a higher MTJ resistance than the parallel state, enabling a read operation by sensing the MTJ resistance difference. The STT-MRAM can have a high integration density exceeding twice that of conventional static RAM [11]. Furthermore, STT-MRAM effectively curtails the overall power consumption by obviating leakage concerns due to the nonvolatility of MTJ [10].

Despite its favorable features, STT-MRAM raises two points of concern regarding its reliability. First, the read current path aligns with the write current path, as illustrated in Figure 1b, introducing a compromise between read stability and writability. For example, a wider access transistor width, which ensures reliable write operations, increases the vulnerability to unintended bit flips during read operations, commonly referred to as read-disturb failures (Figure 1c) [9]. Second, achieving a high-speed write operation necessitates the application of a substantial electrical current, exposing the tunneling oxide barrier to significant stress conditions [11].

Recently, spin-orbit torque magnetic random-access memory (SOT-MRAM) has emerged as an alternative on-chip memory solution, demonstrating enhanced reliability [11,12,13,14,15,16,17,18,19,20,21]. The three-terminal configuration of SOT-MRAM segregates the write and read paths, enabling independent optimization of the read stability and writability [15]. Additionally, in SOT-MRAM, the write mechanism circumvents the need for imposing high stress on the tunneling oxide barrier. Instead, it leverages spin injection from a heavy metal (HM) [11]. Furthermore, in contrast to STT-MRAM, SOT-MRAM holds more potential for energy-efficient write operations, attributed to its high efficiency in spin current injection [17,18].

However, a primary drawback of SOT-MRAM lies in its demand for two access transistors per individual cell, consequently leading to a large cell area footprint [15,22]. Many prior research endeavors have been dedicated to mitigating the cell area problem in SOT-MRAM. These efforts can be classified into two distinct categories: reduction in the (1) vertical dimension and (2) the horizontal dimension. In [22], the read transistor is replaced by a diode selector to reduce the vertical dimension of SOT-MRAM. Joint two-transistor-based SOT-MRAM in [23] is also proposed to enhance the vertical dimension by sharing diffusion regions with adjacent cells. The research on reducing the horizontal dimension is focused on decreasing the number of metal lines routed in vertical dimensions, such as the bit line (BL) and source line (SL). Sharing source-line SOT-MRAM architecture is also proposed in [5] to improve the horizontal dimension. In [15], the horizontal dimension can be reduced by routing the SL in the horizontal direction.

However, to the best of the authors’ knowledge, no study has achieved an extremely high-density SOT-MRAM design by reducing the vertical and horizontal dimensions simultaneously for last-level cache application. This paper aims to discover an improved solution that synergizes two existing strategies, in the vertical and horizontal directions, to achieve a density that exceeds that of STT-MRAM. Specifically, we substitute the conventional read access transistor of SOT-MRAM with a Schottky diode, reducing the requirement to a single access transistor per cell. While this approach for vertical area reduction was initially introduced in [22], the memory cell layout involved a single-finger transistor. In this work, we delve deeper into the influence of the finger count on cell density. We further enhance the memory cell area by introducing the design technique of SL sharing to reduce the horizontal dimension [23]. In addition, as two design techniques were introduced into one high-density cell design, the biasing conditions required for the write and read were also determined to be appropriate for the proposed memory cell. The simulation results indicate that the proposed design can improve the memory cell area by 63% compared with the conventional SOT-MRAM at the identical specification of 10-ns switching time, 10% write margin, and >50% read-disturb margin. Even compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density.

The remainder of this paper is structured as follows. Section 2 provides an overview of the SOT-MRAM principles, and Section 3 introduces the proposed design techniques to enhance the cell area. The simulation results are presented in Section 4, and Section 5 concludes the paper.

2. Conventional SOT-MRAM Design

A three-terminal SOT device (as shown in Figure 2a) is composed of the MTJ and HM. During a write operation, a charge current is applied through the HM, which is in direct contact with the FL. At the bottom part of Figure 2a, the initial alignment of the FL magnetization points in the +y direction. When a charge current is applied in the −x direction, the spin-orbit interaction within the HM generates −y and +y-directed spins toward the upper and lower surfaces of the HM, respectively [17]. The spin-polarized electrons accumulate on the upper surface and exert STT, inducing a switch in the FL magnetization toward the −y direction [18]. The efficiency of the spin current injection can surpass 100% because a single electron traversing through the HM transfers multiple units of angular momentum [17,24,25]. Thus, SOT-MRAM is capable of a low-power write operation. Moreover, this SOT switching mechanism results in the higher reliability of the MTJ due to the absence of substantial stress on its oxide layer from high voltage drops [10,22].

For a read operation, the BL is biased at the read voltage (V_READ), the SL is held at the ground level, and the read word-line (RWL) is activated, as depicted in Figure 2b,c. This biasing condition allows a small current to flow from terminal T₁ to terminal T₃ of the SOT device, facilitating the sensing of stored data by comparing it with the current from a reference cell. Figure 2b displays the separation of the write and read paths, permitting independent optimization of each memory operation without interference [5,15].

However, the SOT-MRAM cell necessitates two access transistors, TR_W for a write operation and TR_R for a read operation. Therefore, the bit-cell area occupied by the SOT-MRAM is larger than for STT-MRAM. Figure 3 shows the SOT-MRAM cell layout, where λ represents half of the minimum feature size. This paper assumes that the minimum metal width and spacing are 3λ [26,27]. Additional design parameters are illustrated in Figure 3a [5,26]. The word-lines (WWL for writing and RWL for reading) are placed horizontally, while the BL and SL run perpendicular to the word-lines. The width of TR_W and TR_R is denoted as W_TR-W and W_TR-R, respectively. If both TR_W and TR_R are designed to be smaller than 9λ, as depicted in Figure 3b (i.e., if max(W_TR-R, W_TR-W) < 9λ), then the horizontal dimension becomes constrained by the metal pitch as follows:

$$2W_{M2M}+2W_M=12\lambda$$

Otherwise, as depicted in Figure 3c, the horizontal dimension is defined by the greater value between W_WFET and W_RFET, as indicated below:

$$max\left(W_{TR\text{-}W}, W_{TR\text{-}R}\right)+W_{A2A}=max\left(W_{TR\text{-}W},W_{TR\text{-}R}\right)+3\mathsf{\lambda }$$

The vertical dimension of SOT-MRAM is

$$W_C+4W_{G2C}+2W_G+2W_C+2W_{C2A}+W_{A2A}=23\mathsf{\lambda }$$

Due to the two-transistor requirement, which is up to 50% larger than the vertical dimension of STT-MRAM [26].

3. Proposed SOT-MRAM Design

First, we implemented a diode instead of a read access transistor to the conventional SOT-MRAM (Figure 4a) to reduce vertical dimensions, as depicted in Figure 4b. In the SOT-MRAM, the write operation requires bidirectional current flows from the BL to SL for writing ‘1’ and from SL to BL for writing ‘0’. Therefore, a transistor is needed that can flow current in both directions. However, the current flows only from the SL to BL for the read operation, so the read access transistor can be replaced with a diode. A single transistor determined the proposed memory cell area by using a Schottky diode capable of integrating into the back-end process proposed in [28]. Hence, the vertical dimension of the proposed cell can be half that of the conventional memory cell.

To further improve the memory cell area, we propose a design technique to reduce the horizontal dimension of the single-transistor-based SOT-MRAM. Assuming that the width of the transistor is small enough, the horizontal dimension is determined by the space for two vertically routed metals. Thus, the horizontal dimension can decrease by reducing the number of vertically routed metals per memory cell. To achieve this, the odd column cell was flipped to combine SL[k] for the odd column cell and SL[k+1] for the even column cell into a single SL, as presented in Figure 4c. This method decreased the number of metals per the two memory cells from four to three, reducing the horizontal dimension by up to 25%.

Figure 5a presents the write and read biasing condition of the odd- and even-column cells in the case of two-bit-interleaved architecture. The bit-interleaving method is widely employed [29,30] to mitigate the potential for multi-bit errors resulting from radiation events. Figure 5b,c depicts instances of write and read operations employing a distance two-bit-interleaving design, where two adjacent BLs, specifically BL [k] and BL [k+1], with k being an odd number, are multiplexed. When the vertical metal line is shared, concurrently conducting a write operation on the odd- and even-column cells becomes infeasible. However, simultaneous access to two adjacent cells is avoided in the bit-interleaving architecture. Hence, the proposed design does not introduce performance overhead.

Since a single SL is utilized for two adjacent cells, it becomes crucial to apply the appropriate bias to a pair of cells to ensure that accessing one cell for memory operations does not interfere with the other cell connected to the same SL. For example, when writing a ‘0’ value into an odd-column cell, as shown in Figure 5b, SL[k+2] is applied to V_WRITE, BL[k+2] is grounded, and WWL is activated, enabling current flow from SL[k+2] to BL[k+2]. In addition, V_WRITE is applied to BL[k+3] to prevent unintended overwriting of the even column cell. In addition, during the write operation, the Schottky diode remains in a reverse-biased state, preventing sneak current flow. As illustrated in Figure 5c, RWL is supplied with V_READ, and BL[k+1] and BL[k+3] are connected to the ground during the read operation for even-column cells. Thus, the diode is forward-biased, and the read current flows from RWL to BL[k+1] and BL[k+3].

Figure 6a,b reveals the layout designs for the proposed ultra high-density MRAM using a single-finger transistor. The vertical dimension of the proposed memory cell is half that of the conventional SOT-MRAM cell, determined by the subsequent formula:

$$0.5W_C+2W_{G2C}+W_G+W_C+W_{C2A}+0.5W_{A2A}=11.5\mathsf{\lambda }$$

When W_TR is designed to be smaller than 6λ, the horizontal dimension is in the metal pitch Limited (MPL) region and the metal spacing establishes the horizontal dimension, as illustrated in Figure 6a:

$$2W_{M2M}+W_M=9\lambda$$

Otherwise, as depicted in Figure 6b, the horizontal dimension is in the transistor width limited (TWL) region, and the transistor width defines the horizontal dimension as follows:

$$W_{TR}+W_{A2A}=W_{TR}+3\mathsf{\lambda }$$

Figure 6c,d illustrates the proposed memory cell layouts employing a two-finger transistor. In this layout design using two-finger transistors, the SL contact of the cell can be shared with two neighboring cells within the same column. The space for separating a diffusion region can be eliminated. Thus, the optimal memory cell area can be obtained in the two-finger-based design rather than the single-finger-based design when W_TR > 9.5λ. The vertical dimension of the two-finger transistor layout is given by:

$$2W_C+4W_{G2C}+2W_G=16\mathsf{\lambda }$$

When W_TR is smaller than 12λ, the horizontal dimension is 9λ, limited by the metal pitch in Figure 6c. In contrast, the horizontal dimension is defined by a diffusion region of the transistor rather than the metal pitch as follows (Figure 6d):

$$0.5W_{TR}+W_{A2A}=0.5W_{TR}+3\mathsf{\lambda }$$

Figure 7 compares the area of STT-MRAM, conventional SOT-MRAM, and the proposed MRAM according to the transistor width. The proposed ultra-high-density version of SOT-MRAM displays an area savings of 65% over conventional SOT-MRAM in the MPL region. Even compared to STT-MRAM, the area in the MPL area is 25% smaller using the horizontal dimension reduction technique. Unlike conventional SOT-MRAM, the proposed memory can further optimize the area using a fingered transistor if the transistor width exceeds 9.5λ. Therefore, when the larger size of the transistor is required for design specification, the greater the area efficiency can be achieved compared to conventional SOT-MRAM by using a two-finger transistor.

4. Simulations and Results

To evaluate the effectiveness of the proposed memory design for comparison with STT-MRAM and conventional SOT-MRAM, we employed a simulation framework [31] encompassing four components:

• A solver for the Landau–Lifshitz–Gilbert equation was used to model the magnetization dynamics of the spintronic devices [32,33].
• The nonequilibrium Green’s function formalism deduces the resistivity of the MTJ [31,34].
• A Verilog-A model was implemented to acquire the voltage-dependent current characteristics of the Schottky diode [22,28].
• The simulation program integrated circuit emphasis (SPICE) simulator modeled the MRAM bit-cells.

The Landau–Lifshitz–Gilbert equation solver calculates the critical current required for a switching time of 10 ns using the parameters in

Table 1. Parameters for spintronic devices.

Device Parameters	STT Device	SOT Device
Gilbert damping, α	0.007	0.0122
Saturation magnetization, MS	1000 × 103 A/m	1000 × 103 A/m
FL dimension (WFL × LFL × tFL)	120 × 40 × 2 nm a	120 × 40 × 2 nm a
HM dimension (WHM × LHM × tHM)	-	120 × 80 × 2.5 nm
HM resistivity	-	200 µΩ·cm
Spin hall angle, θSH	-	0.3
Spin flip length, λsf	-	1.40 nm
MgO thickness, tMgO	1.15 nm	1.40 nm
Critical current for 10-ns switching time	139 µA	87 µA

^a The FL of MTJ is elliptical. (FL: free layer, HM: heavy metal, STT: spin-transfer torque, SOT: spin-orbit torque.

. For the SOT device, the efficiency of the spin current injection, represented as the ratio of I_S to I_C, can be obtained using the formula [16,25]:

$$\frac{I_S}{I_C}=\frac{A_{MTJ}}{A_{HM}}·{\theta }_{SH}(1-\sec \mathrm{h}(\frac{t_{HM}}{{\lambda }_{sf}}))$$

where A_MTJ refers to the cross-sectional area of the MTJ in the xy-plane, A_HM denotes the cross-sectional area of the HM in the yz-plane, t_HM signifies the thickness of the HM, λ_sf represents the spin-flip length, and θ_SH denotes a spin Hall angle, which we set to 0.3 in the analysis [17]. As A_HM (= W_HM × t_HM) is set smaller than A_MTJ (= π/4 × W_FL × L_FL), the resulting spin current injection efficiency achieves 254%, enabling low current write operation.

The resistance characteristics of the HM are acquired from experimental resistivity data found in [17]. Meanwhile, the voltage-dependent resistance of the MTJ is derived using the nonequilibrium Green’s function formalism, as explained in [10,34]. Additionally, we emulate the behavior of the diode by employing a Verilog-A compact model, where we have successfully calibrated the voltage-dependent current values to match experimental results from a TiO_X-based Schottky diode with a cross-sectional area of 4µm² [28]. To estimate the current flow for the proposed device dimensions (an elliptical shape of 120 × 40 nm), we extrapolate the current density trends observed in experiments with varying cross-sectional areas [22].

By integrating the resistance characteristics of the spintronic device and the model compatible with the SPICE simulator of the Schottky diode with a commercial 45 nm transistor, we conducted transient circuit simulations to evaluate the three distinct memory bit-cells. The design of the three memory bit-cells was executed under identical conditions, including a 10-ns switching time, a 10% write margin (defined as (I_W − I_C)/I_C, where I_W represents the write current and I_C signifies the critical current), and a read-disturb margin of >50% (defined as (I_C − I_R)/I_C, with I_R representing the read current) [5].

Table 2. Comparison of three different memory cells in terms of area, write and read power, and read-disturb margin.

	STT-MRAM	Conventional SOT-MRAM	Proposed SOT-MRAM
Transistor width (nm)	380	120 (WTR-R) 120 (WTR-W)	120
Bit-cell area (µm2)	0.0800	0.1104	0.0414
VWRITE (V)	1.0	0.6	0.6
VREAD (V)	0.2	0.2	0.8
Write power (µW)	193.48	61.08	61.07
Read power (µW)	10.14	1.84	7.21
Read-disturb margin (%)	51	94	95

presents the simulation results. For STT-MRAM, where the paths for both the write and read currents are identical, the size of the access transistor is determined to accommodate write and read operations. The transistor width is 380 nm in the analysis, primarily based on write operation requirements rather than read operations. Owing to its high spin current injection efficiency, the smaller transistor width of 120 nm is sufficient to achieve the same write operation conditions for SOT-MRAM. However, due to the need for an additional transistor for the read, the bit-cell area of conventional SOT-MRAM (0.1104 µm²) is 20% larger than that of STT-MRAM (0.0880 µm²).

In contrast, the proposed SOT-MRAM can mitigate the problem of a longer vertical dimension overhead by replacing the read transistor with the Schottky diode. Moreover, the proposed memory shares an SL between two neighboring memory cells in the same row, resulting in a smaller horizontal dimension than conventional memory. Therefore, the proposed high-density memory cell achieves a 48% smaller area than STT-MRAM.

Importantly, the proposed design preserves the inherent advantages of SOT-MRAM. Thanks to its remarkable spin current injection efficiency, which stands at 254%, our proposed MRAM design reduces write power significantly by 68% when compared to STT-MRAM. Furthermore, unlike STT-MRAM, where the oxide thickness (t_MgO) is constrained by the trade-off between writability and read stability, our proposed design allows the optimization of t_MgO exclusively for read operations. This advantage stems from the fact that the oxide layer does not play a role in the write current path. Consequently, employing a thicker oxide layer becomes feasible, enhancing the read-disturb margin by 1.9× with a 29% improvement in read power. Nevertheless, the proposed MRAM exhibits a higher read power consumption than conventional SOT-MRAM due to the necessity of raising the read voltage to surpass the diode turn-on voltage.

5. Conclusions

This paper proposes an ultra-high-density SOT-MRAM design. Using a diode on the read current path instead of a read access transistor, SOT-MRAM can be a single-transistor-based design such that the vertical dimension can be reduced by up to 50%. Moreover, by combining the SL of two adjacent cells in the same row, a horizontal dimension reduction also can be achieved by up to 25%. The proposed memory cell preserves the benefits of conventional SOT-MRAM, including enhanced reliability and reduced write power. Simulation results reveal that the proposed design technique reduces the bit-cell size by 63% and 48%, compared with STT-MRAM and conventional SOT-MRAM, respectively. In comparison to STT-MRAM, the proposed configuration yields a substantial 68% reduction in write power, a 29% decrease in read power, and a 1.9× improved read-disturb margin.