Analysis and Suppression of Rectifier Diode Voltage Oscillation Mechanism in IPOS High-Power PSFB Converters

Abstract

Parasitic oscillations in the rectifier diode voltage of phase-shifted-full-bridge (PSFB) converters limit their application in high-voltage and high-power situations. The conventional analysis method for parasitic oscillation in rectifier diode voltage in PSFB converters treats the filter inductor as a constant current source and fails to consider the impact of changes in filter inductor current on the rectifier diode’s parasitic oscillation. Consequently, this approach does not apply when analyzing the rectifier diode voltage’s parasitic oscillations in high-power PSFB converters employing an input-parallel output-series (IPOS) configuration with interleaved drive. This research paper introduces an innovative equivalent circuit model for analyzing the parasitic oscillations of rectifier diode voltage in IPOS high-power PSFB converters. The model takes into account the mutual influence of rectifier diode voltage oscillations between submodules under interleaved control, considering the influence of changes in filter inductor current on rectifier diode parasitic oscillation. Based on the circuit model, we explain the mechanism of multiple oscillations of the rectifier diode voltage and the reason for the high peak of the first oscillation. Consequently, the interplay of rectifier diode voltage oscillations in IPOS high-power k-module PSFB converters under interleaved control is analyzed. To mitigate the adverse effects of rectifier diode voltage parasitic oscillation, a buffering strategy involving the connection of a resistor capacitor diode (RCD) circuit in parallel after the rectifier bridge is adopted, considering the structure of the IPOS high-power PSFB converter. The study provides a detailed analysis of the circuit’s operation mechanism upon incorporating the RCD buffer circuit and establishes the relationship between buffer capacitance, resistance, and spike voltage. Furthermore, a design method for buffer capacitors and discharge resistors in buffer circuits is presented. Finally, a 100 kW prototype is tested to verify the rectifier diode voltage oscillation mechanism of the IPOS high-power PSFB converter and the rationality of the buffer capacitor and discharge resistor design method under the interleaved drive approach.

1. Introduction

In light of the escalating depletion of fossil energy resources and the escalating concern regarding global warming, the production of clean energy from sources such as wind and solar power has gained considerable attention [1]. As an important link in the conversion of electrical energy, the reliability, efficiency, and power density of DC converters play a key role in the efficient use of clean energy [2]. Zero-voltage switching (ZVS) PSFB converters are the most commonly used topologies in the medium-to-high-power range [3,4,5]. The main attractive features compared to resonant converters [6,7,8] are the ZVS switching of the primary switching transistor, the constant switching frequency, and the simplicity of the control [9]. Nevertheless, the conventional PSFB ZVS pulse-width modulated (PWM) converters have severe parasitic oscillations and high spike voltages on the output rectifier diode due to the filter inductor decoupling the rectifier stage from the capacitor stage, making the junction capacitor of the rectifier diode a passive buffer. Consequently, the rectifier diode will be subjected to high voltage and current stresses, which become particularly severe in medium and high voltage, high power applications [10].

The suppression of the rectifier diode spike voltage of the PSFB converter determines the success or failure of the entire converter design in high-voltage and high-power applications. The operating conditions of the switching transistors and rectifier diodes would be very harsh if only a single PSFB converter module was used. The DC/DC converter structure with multiple modules interleaved in parallel solves this problem well. By connecting the modules in series or parallel to the input terminal, voltage and current equalization between individual modules can be achieved, respectively. Moreover, the combination of serial and parallel connections to the output terminal allows for higher output voltages and higher output currents, respectively, and each connection method has its own characteristics, application areas, and advantages [11]. In addition, using redundant modules can improve the reliability of the modular conversion system [12]. The high boost ratio and high conversion efficiency of IPOS structures make them widely used in energy storage, renewable energy generation, and high-voltage pulse generators [13,14].

Many scholars have proposed many methods to suppress the problem of rectifier diode spike voltage in conventional PSFB converters. The literature [15] analyzed in detail the mechanism of rectifier diode spike voltage generation in a conventional phase-shifted full-bridge converter and proposed a basic method to suppress rectifier diode voltage oscillations. In the literature [16,17], the parasitic oscillation of the rectifier diode is well suppressed by adding a resonant inductor and clamp diode to the primary side and changing the driving mode of the switching transistor appropriately. However, by adding a clamp diode to the inverter bridge arm, only the additional inductance and rectifier diode junction capacitance oscillations can be suppressed. In contrast, the leakage inductance of the high-power, high-frequency transformer is difficult to reduce. The literature [18] regulates the effective energy of ZVS by introducing a triple-winding coupled inductor in the inverter bridge arm, thus reducing the need for an output filter inductor and the parasitic oscillation of the rectifier diode. However, the design of the triple-winding coupled inductor is complicated, and the loss of the triple-winding coupled inductor is high in high-power and high-voltage ratio applications. The analysis method of the rectifier diode voltage oscillation mechanism of the traditional PSFB converter is not applicable to the IPOS high-power PSFB converter under interleaved control, and the parasitic oscillations in the rectifier diode voltage of the IPOS high-power PSFB converter under interleaved control are more complex, making these solutions more difficult to implement in this converter.

This paper presents a novel approach to developing an equivalent circuit model for analyzing the parasitic oscillation of rectifier diode voltage in an IPOS high-power PSFB (phase-shifted full-bridge) converter with interleaved drive. The study takes into account the impact of changes in filter inductor current on the parasitic oscillation of the rectifier diode and aims to enhance the accuracy of the corresponding model. It is analyzed in detail to determine the mutual effect of rectifier diode voltage oscillation between submodules of an IPOS converter composed of two PSFB submodules under interleaved drive. The paper elucidates the mechanism behind the three oscillations of the rectifier diode voltage and provides an explanation for the high peak observed in the first oscillation. Furthermore, it proposes an oscillation mechanism for the rectifier diode voltage in the IPOS high-power k-module PSFB converter under interleaved control. To suppress the adverse effects of the parasitic oscillations of the rectifier diode voltage, the buffering strategy of shunt RCD after the rectifier bridge is chosen in conjunction with the structure of the IPOS high-power PSFB converter. Analyzing the relationship between buffer capacitor and discharge resistor with spike voltage and proposing the design method of buffer capacitor and discharge resistor. The correctness of the voltage oscillation mechanism of the rectifier diode of the IPOS high-power PSFB converter and the rationality of the design method of the buffer capacitor and discharge resistor in the buffer circuit is verified through experiments.

The paper is organized according to the following structure: In Section 2, the equivalent circuit of the parasitic oscillation of rectifier diode voltage in the IPOS high-power PSFB converter is established. The mechanism of the parasitic oscillation of rectifier diode voltage under interleaved control is analyzed in detail. Additionally, it also presents the mechanism of n + 1 oscillations of the rectifier diode voltage in the IPOS high-power PSFB converter, which is based on n sub-modules. Section 3 describes the operation of the buffer capacitor after adding the RCD buffer circuit to a single submodule in the IPOS high-power PSFB converter and gives the design method of RC. In Section 4, a 100 kW hardware converter prototype is designed, manufactured, and tested to verify the correctness of the rectifier diode voltage oscillation mechanism and the rationality of the RC design method for the buffer circuit. Finally, conclusions are given in Section 5.

2. Mechanism of Rectifier Diode Voltage Oscillation

The conventional PSFB converter considers the junction capacitance of the rectifier diode to simulate the reverse recovery of the rectifier diode, and its main circuit is shown in Figure 1. S₁~S₄ are the four switching transistors of the primary inverter H-bridge. If the driving signals of S₁ and S₃ are ahead of S₂ and S₄, respectively, the bridge arms in which S₁ and S₃ are located are said to be ahead of the bridge arms, and the bridge arms in which S₂ and S₄ are located are said to be lagging bridge arms. D_S1~D_S4 and C₁~C₄ are the switching transistor’s internal anti-parallel diodes and the junction capacitance, respectively. $v_{AB}$ is the output square wave AC voltage of the inverter bridge arm, and $L_r$ is the resonant inductor of the primary side. The ZVS of the switching transistor is achieved by using the resonant inductor of the primary side (or transformer leakage) and the junction capacitance of the switching transistor to resonate [19,20,21]. T_r for high-frequency transformer primary and secondary turns ratio is 1:n, * is the eponymous end of the transformer, $i_p$ for transformer primary current, and $C_b$ is the isolation capacitor to prevent DC bias of the high-frequency transformer. D₁~D₄ are the secondary rectifier diodes; $C_{j1}~C_{j4}$ are the junction capacitors of the rectifier diodes; $V_{rect}$ is the rectified H-bridge output voltage; $L_f$ and $C_f$ are the filter inductor and filter capacitor, respectively; $i_{Lf}$ is the current flowing through the filter inductor; $V_{in}$ and $C_{in}$ are the input voltage and input filter capacitor, respectively; $R_L$ and $V_o$ are the load resistance and output voltage, respectively.

When considering the junction capacitance of the rectifier diode, the resonance of the primary resonant inductor with the diode junction capacitance during the switching transistor hysteresis bridge arm commutation subjects the diode to a very high spike voltage. The resonant energy comes from the imbalance between the primary resonant inductor and the filter inductor current. The maximum values of the transformer primary-side current and rectifier diode voltage, $i_{pmax}\left(t\right)$ and $v_{Cj23max}\left(t\right)$, are, respectively [15]:

$$i_{pmax}(t)=n{i}_{Lf}(t)+V_{in}\sqrt{\frac{C_{j23}}{L_r}}$$

(1)

$$v_{Cj23max}(t)=2n{V}_{in}$$

(2)

$C_{j23}$ is the parallel equivalent capacitance of the diagonal diode parasitic capacitance $C_{j2}$ and $C_{j3}$ of the rectifier bridge, and $v_{cj23}$ is the voltage across the parallel equivalent capacitance. Combined with Equation (2), if the resonant inductor and filter inductor are respectively equivalent to a current source, the components of the primary side of the transformer are converted to the secondary side to further simplify the equivalent circuit, as shown in Figure 2. The essence of the resonant inductor and diode junction capacitance resonance generating diode spike voltage is the current imbalance between the primary equivalent current source of the transformer and the secondary equivalent current source of the transformer. That is, the current of the primary equivalent current source is greater than that of the secondary equivalent current source. This excess current charges the capacitance at the commutation point between the secondary and diode, leading to oscillation in the primary resonant inductor and rectifier diode junction capacitance.

The IPOS high-power PSFB converter module is composed of multiple PSFB converter submodules connected in series after rectification at the output side in parallel with the input side [22]. Taking an IPOS high-power PSFB converter composed of two submodules as an example, the main circuit shown in Figure 3a takes into account the rectifier diode junction capacitance. $L_{r1}$ and $L_{r2}$, $C_{b1}$ and $C_{b2}$, $i_{p1}$ and $i_{p2}$, $V_{rect1}$ and $V_{rect2}$, and T_r1 and T_r2 are the resonant inductors (or transformer leakage), bulkhead capacitors, primary side currents, rectified output voltages, and transformers of submodules M₁ and M₂, respectively. $V_{in}$, $C_{in}$, $V_{rect}$, $L_f$, $C_f$, $i_{Lf}$, $R_L$, and $V_o$ are the input voltage, input capacitance, rectified output voltage, filter inductor, filter capacitor, current flowing through the filter inductor, load equivalent resistance, and output voltage of the IPOS high-power PSFB converter module (hereinafter referred to as the module), respectively.

Defining the primary duty cycle D as the ratio of the overlap time of diagonal switching transistors to the switching period within one switching cycle. When neglecting all resonant modes and considering the PSFB converter as an isolated buck converter, its effective duty cycle $D_{eff}$ on the secondary side is [23]:

$$D_{eff}=\frac{V_o}{2n{V}_{in}}$$

(3)

Typically, to achieve greater power transfer and higher boost ratios, IPOS high-power PSFB converters are designed for stable operation with an effective duty cycle of $D_{eff}>0.5$ on the secondary side. For reducing the input and output voltage and current ripple, interlaced driving is usually used between submodules. Figure 3b shows the main waveforms of the IPOS high-power PSFB converter for $D_{eff}>0.5$ under interleaved drive. Since two rectifier H-bridges of this converter share a set of output LC filter networks, the interleaved driving mode makes the voltage oscillation process of the rectifier diode more complicated, and the parasitic oscillation of the rectifier diode of the IPOS high-power PSFB converter will be more serious compared with the adverse effect brought by the parasitic oscillation of the rectifier diode of a traditional PSFB converter.

When the circuit is operating in a steady state, take submodule M₁ as an example to analyze the effect of submodule M₂ rectifier diode commutation on submodule M₁ rectifier diode voltage oscillation under interleaved control. The following assumptions are made for the convenience of the analysis [24,25]:

(1)

The output voltage V_o is constant with a large filter capacitor, and $V_{rect1}<V_o$, $V_{rect2}<V_o$, $n{V}_{in}<V_o$, $2n{V}_{in}>V_o$, and $V_{rect1}+V_{rect2}>V_o$ when the circuit is operating in a steady state and both $V_{rect1}$ and $V_{rect2}$ are non-zero, as shown in Figure 3b;

(2)

the resonant inductance of the primary side of submodules M₁ and M₂ is equal, and the junction capacitance of all rectifier diodes is equal, i.e., $L_{r1}=L_{r2}=L_r$, $C_{j1}=C_{j2}=\dots =C_{j8}$;

(3)

compared to the resonant inductance, the filter inductance is much larger, i.e., $L_f>>L_r$.

2.1. First Oscillation of Rectifier Diode Voltage

Before the moment $t_1$ in Figure 3b, the switching transistors S₆ and S₇ and rectifier diodes D₆ and D₇ of submodule M₂ are in conduction, and the rectifier output voltage is $V_{rect2}$. The switching transistors S₁ and S₄ of submodule M₁ are in the conduction state, and since their primary current is less than the converted value of the secondary current, the secondary rectifier diodes are all on to renew the current. The rectifier output voltage of submodule M₁ $V_{rect1}=0$. All input voltage is added to the resonant inductor $L_{r1}$, resulting in a linearly increasing primary current. At this time, only submodule M₂ supplies power to the load; the module rectification output voltage $V_{rect}=V_{rect2}$. The current value $i_{Lf}$ flows through the filter inductor as:

$$i_{Lf}(t)=i_{Lf}(t_0)+\frac{n{V}_{in}-V_o}{n^2{L}_{r2}+L_f}(t-t_0)$$

(4)

In Equation (4), the filter inductor current decreases linearly before $t_1$. The primary side current of submodule M₂ is the same as the converted value for the secondary side current, which decreases linearly as well. At the moment $t_1$, the primary current of submodule M₁ increases to a converted value equal to the secondary current. The resonant inductor $L_{r1}$ resonates with the junction capacitors $C_{j2}$ and $C_{j3}$ of rectifier diodes D₂ and D₃, charging the junction capacitors $C_{j2}$ and $C_{j3}$. The rectified output voltage of submodule M₁ is equal to the voltage of junction capacitors $C_{j2}$ and $C_{j3}$, and the primary side current $i_{p1}$ of submodule M₁ before $V_{rect1}$ rises to $V_o-V_{rect2}$, i.e., before the $t_2$ moment, is:

$$i_{p1}(t)=i_{p1}(t_1)+\frac{V_{in}-V_{rect1}/n}{L_{r1}}(t-t_1)$$

(5)

The filter inductor current $i_{Lf}$ is:

$$i_{Lf}(t)=i_{Lf}(t_1)+\frac{V_{rect}-V_o}{L_f}(t-t_1)$$

(6)

In Equations (5) and (6), the primary side current of submodule M₁ is increasing and the filter inductor current is decreasing in the period [$t_1$–$t_2$]. Nevertheless, the primary current of the submodule M₁ is already equal to the converted value of the filter inductor current at the moment $t_1$. This causes an imbalance in the primary and secondary currents of submodule M₁, making the primary current greater than the converted value of the secondary current and generating the first oscillation of the rectifier diode D₂ and D₃ voltages. At this stage, the primary current comprises two components: one corresponds to the filter inductor current converted to the secondary side, and the other component represents the resonant current resulting from the resonant operation between the resonant inductor and the junction capacitor.

The components on the primary side of the transformer are equated to the secondary side to analyze the interaction of the rectified output voltage between the IPOS high-power PSFB converter modules. Since the output filter capacitor is large, the output filter capacitor and load branch are replaced with a constant voltage source $V_o$ for simplicity of analysis. The equivalent circuit for the [$t_1$–$t_3$] period is drawn in Figure 4.

In Figure 4, $n{V}_{in}$ is the equivalent value of the input supply voltage converted to the secondary side; $i_{p1}/n$, $i_{p2}/n$ and $n^2{L}_{r1}$ and $n^2{L}_{r2}$ are the equivalent values of the primary side current and resonant inductance of submodules M₁ and M₂ converted to the secondary side. The capacitances $C_{j23}$ and $C_{j58}$ are the equivalent capacitances of rectifier diode junction capacitor $C_{j2}$ in parallel with $C_{j3}$ and the equivalent capacitances of $C_{j5}$ and $C_{j8}$ in parallel, respectively. The differential equation of Figure 4 is written and substituted into the initial conditions to solve the expressions of $i_{p1}$ and $v_{cj23}$ for the period [$t_1$–$t_2$] as:

$$i_{p1}(t)=n{i}_{Lf}(t-t_1)+n{V}_{in}\sqrt{\frac{C_{j23}}{n^2{L}_{r1}}}\sin {\omega }_1\frac{(t-t_1)}{\sqrt{C_{j23}{n}^2{L}_{r1}}}+\frac{V_o-n{V}_{in}}{n^2{L}_{r2}+L_f}(t-t_1)$$

(7)

$$v_{cj23}(t)=\frac{n^2{L}_{r2}+L_f}{n^2(L_{r2}+L_{r1})+L_f}n{V}_{in}\left[1-\cos \frac{(t-t_1)}{\sqrt{n^2{L}_{r1}{C}_{j23}}}\right]+\frac{n^2{L}_{r1}}{n^2(L_{r1}+L_{r2})+L_f}\left[V_o-n{V}_{in}+\frac{n^2{L}_{r1}(V_o-n{V}_{in})}{n^2(L_{r1}+L_{r2})+L_f}\cos {\omega }_2\frac{(t-t_1)}{\sqrt{n^2{L}_{r2}{C}_{j58}}}\right]$$

(8)

The first oscillation of the rectifier diode causes the rectified output voltage of submodule M₂ to transition from $V_{rect2}>n{V}_{in}$ to $V_{rect2}<n{V}_{in}$ after moment $t_1$. The primary side current $i_{p2}$ of submodule M₂ transitions from a linear decrease before moment $t_1$ to a linear increase after moment $t_1$ in line with the filter inductor current $i_{Lf}$.

2.2. Second Oscillation of Rectifier Diode Voltage

Before the moment $t_3$ in Figure 3b, the switching transistors S₁ and S₄ and rectifier diodes D₁ and D₄ of submodule M₁ are in conduction, and the rectifier output voltage is $V_{rect1}$. The switching transistors S₆ and S₇ and rectifier diodes D₆ and D₇ of submodule M₂ are also in conduction, and the rectified output voltage is $V_{rect2}$. The rectified output voltages of submodules M₁ and M₂ are constant together to supply the load. The rectified output voltage of the module is $V_{rect}=V_{rect1}+V_{rect2}$, and the current value $i_{Lf}$ flowing through the filter inductor is:

$$i_{Lf}(t)=i_{Lf}(t_3)+\frac{2n{V}_{in}-V_o}{2n^2(L_{r1}+L_{r2})+L_f}(t-t_3)$$

(9)

In Equation (9), the filter inductor current increases linearly before the $t_3$ moment, and the primary side currents of submodules M₁ and M₂ are equal to the converted value of the filter inductor current, which also increases linearly. At the moment $t_3$, the switching transistor S₇ turns off, and the rectified output voltage of submodule M₂ starts to drop. When the rectified output voltage of submodule M₂ drops to $V_{rect2}<V_o-V_{rect1}$, i.e., at moment $t_4$, the filter inductor current $i_{Lf}$ is:

$$i_{Lf}(t)=i_{Lf}(t_3)+\frac{V_{rect}-V_o}{L_f}(t-t_4)$$

(10)

In Equation (10), the filter inductor current starts to decrease linearly after moment $t_4$, while the primary side current $i_{p1}$ of submodule M₁ keeps increasing linearly in line with that before moment $t_3$. This causes an imbalance in the primary and secondary currents of submodule M₁, making the primary current of submodule M₁ greater than the converted value of the secondary current. A second oscillation of the rectifier diode D₂ and D₃ voltages is generated. The second oscillation of the rectifier diode voltage causes the rectifier output voltage of submodule M₁ to transition from $V_{rect1}<n{V}_{in}$ to $V_{rect1}>n{V}_{in}$ after moment $t_4$, and the primary side current $i_{p1}$ of submodule M₁ is:

$$i_{p1}(t)=i_{p1}(t_4)+(\frac{n(n{V}_{in}-V_o)}{n^2{L}_{r1}+L_f})(t-t_4)$$

(11)

This means that the second oscillation causes the average value of the rectified output voltage of submodule M₁ to increase, so that the primary current $i_{p1}$ of submodule M₁ decreases linearly with the same filter inductor current $i_{Lf}$. Similar to the analysis in Section 2.1, its equivalent circuit in the period [$t_3$–$t_5$] is shown in Figure 5.

When the switching transistor S₇ is turned off, it is considered that the rectifier output voltage $V_{rect2}$ of submodule M₂ decreases linearly, and the expressions $i_{p1}$ and $v_{cj23}$ can be obtained as:

$$i_{p1}=n{i}_{Lf}(t-t_3)+\frac{n^2{L}_{r1}(2n{V}_{in}-V_o)}{\left[2n^2(L_{r1}+L_{r2})+L_f\right]}\sqrt{\frac{C_{j23}}{n^2{L}_{r1}}}\sin {\omega }_1(t-t_3)$$

(12)

$$v_{cj23}=\frac{n^2{L}_{r2}+L_f}{n^2(L_{r1}+L_{r2})+L_f}\left[n{V}_{in}+\frac{n^2{L}_{r1}(V_o-2n{V}_{in})}{n^2(L_{r1}+L_{r2})+L_f}\cos \frac{(t-t_3)}{\sqrt{n^2{L}_{r1}{C}_{j23}}}\right]+\frac{n^2{L}_{r1}}{n^2(L_{r1}+L_{r2})+L_f}\left[V_o-\left(n{V}_{in}-\frac{i_{Lf}(t-t_3)}{C_{j58}+2n^2{C}_5}\right)\right]$$

(13)

2.3. Third Oscillation of Rectifier Diode Voltage

Before the moment $t_6$ in Figure 3b, the switching transistors S₁ and S₄ and rectifier diodes D₁ and D₄ of submodule M₁ are in the conduction state, and the rectifier output voltage is $V_{rect1}$. The switching transistors S₅ and S₈ of submodule M₂ are in conduction, but since their primary current is less than the converted value of the secondary current, the secondary rectifier diodes are all on to renew the current, and the rectifier output voltage of submodule M₂ is $V_{rect2}=0$. The input voltage is all added to the resonant inductor $L_{r2}$, and the primary current increases linearly. At this time, only the submodule M₁ supplies power to the load; the module rectification output voltage $V_{rect}=V_{rect1}$, and the current value $i_{Lf}$ flowing through the filter inductor is:

$$i_{Lf}(t)=i_{Lf}(t_6)+\frac{n{V}_{in}-V_o}{n^2{L}_{r1}+L_f}(t-t_6)$$

(14)

In Equation (14), the filter inductor current decreases linearly before the moment $t_6$, and the primary side current of submodule M₁ is equal to the converted value of the filter inductor current, which also decreases linearly. At the moment $t_6$, the primary current of submodule M₂ increases to a value equal to the converted value of the secondary current, at which time the resonant inductor $L_{r2}$ resonates with the junction capacitors $C_{j6}$ and $C_{j7}$ of rectifier diodes D₆ and D₇, charging the junction capacitors of the diodes. The diode voltage starts to rise, and the rectified output voltage of submodule M₂ is equal to the voltage of junction capacitors $C_{j6}$ and $C_{j7}$, which also starts to rise. When $V_{rect2}$ rises to $V_{rect2}>V_o-V_{rect1}$, i.e., at the moment $t_7$. The current $i_{Lf}$ of the filter inductor is:

$$i_{Lf}(t)=i_{Lf}(t_7)+\frac{V_{rect}-V_o}{L_f}(t-t_7)$$

(15)

In Equation (15), the filter inductor current starts to increase after moment $t_7$, while the primary current $i_{p1}$ of submodule M₁ keeps decreasing linearly in line with that before moment $t_6$, making the primary current of submodule M₁ smaller than the converted value of the secondary current and transformer T_r1 lose carrying capacity. The rectifier diode junction capacitors $C_{j2}$ and $C_{j3}$ of submodule M₁ start to discharge, the rectifier output voltage $V_{rect1}$ starts to decrease, and the transformer primary side voltage also starts to decrease. At the moment $t_8$, the transformer’s primary voltage is less than the input voltage. At this time, the primary current $i_{p1}$ of submodule M₁ is:

$$i_{p1}(t)=i_{p1}(t_8)+\frac{V_{in}-V_{rect1}/n}{L_r}(t-t_8)$$

(16)

In Equation (16), the primary current $i_{p1}$ of submodule M₁ starts to increase after $t_8$ moments. Due to the small resonant inductance, the primary current rises rapidly. The primary current of submodule M₁ rises to a converted value equal to the secondary current at $t_9$ moments, and transformer T_r1 recovers its carrying capacity. Since the junction capacitors $C_{j2}$ and $C_{j3}$ of the rectifier diode have been discharged during the [t₇–t₉] period, the primary and secondary windings of transformer T_r1 lose contact, so there is a loss of duty cycle during the [t₇–t₉] period. The primary current of submodule M₁ is equal to the converted value of the secondary current at $t_9$, but the primary current of submodule M₁ still rises rapidly because the discharge of the junction capacitors C_j2 and $C_{j3}$ of the rectifier diode makes $V_{rect1}$ less than $n{V}_{in}$. Thus, there is an imbalance of the primary and secondary currents of submodule M₁, which makes the primary current of submodule M₁ larger than the converted value of the secondary current, resulting in the third oscillation. The third oscillation of the rectifier diode causes the rectified output voltage of submodule M₁ to transition from $V_{rect1}>n{V}_{in}$ to $V_{rect1}<n{V}_{in}$ after moment $t_9$. The primary side current $i_{p1}$ of submodule M₁ is:

$$i_{p1}(t)=i_{p1}(t_9)+\frac{n(2n{V}_{in}-V_o)}{2n^2(L_{r1}+L_{r2})+L_f}(t-t_9)$$

(17)

The third oscillation causes the average value of the rectified output voltage of submodule M₁ to decrease. The transformer primary voltage of sub-module M₁ is less than the input voltage $V_{in}$, which makes the primary current $i_{p1}$ of sub-module M₁ rise linearly and the filter inductor current $i_{Lf}$ remain the same. Similar to the equivalent in Section 2.1, its equivalent circuit for the period [$t_6$–$t_{10}$] is shown in Figure 6.

From Figure 4 and Figure 6, it can be seen that the equivalent circuit structure of the third oscillation and the first oscillation of the rectifier diode D₂ or D₃ voltage are the same. This is because submodules M₁ and M₂ are symmetrical, and the first oscillation occurs in the rectifier bridge arm commutation of submodule M₁, while the third oscillation occurs in the rectifier bridge arm commutation of submodule M₂. Since the submodules M₁ and M₂ operate symmetrically, their equivalent circuits are the same. Similarly, in the period [$t_6$–$t_{10}$] from Figure 6, we can obtain $i_{p1}$ and $v_{cj23}$ as:

$$i_{p1}=n{i}_{Lf}(t-t_6)+\frac{n^2{L}_{r1}(n{V}_{in}-V_o)}{(n^2{L}_{r1}+L_f)}\sqrt{\frac{C_{j23}}{n^2{L}_{r1}}}\sin {\omega }_1\frac{(t-t_6)}{\sqrt{n^2{L}_{r1}{C}_{j23}}}$$

(18)

$$v_{cj23}=\frac{L_{r2}+L_f}{L_{r1}+L_{r2}+L_f}\left[n{V}_{in}+\frac{n^2{L}_{r1}(V_o-n{V}_{in})}{n^2{L}_{r1}+L_f}\cos {\omega }_1\frac{(t-t_6)}{\sqrt{n^2{L}_{r1}{C}_{j23}}}\right]+\frac{L_{r1}}{L_{r1}+L_{r2}+L_f}\left[V_o-n{V}_{in}(1-\cos {\omega }_2\frac{(t-t_6)}{n^2{L}_{r2}{C}_{j67}})\right]$$

(19)

2.4. k + 1 Oscillations of k PSFB Submodules

To achieve higher power transfer and a higher step-up ratio, more PSFB converter submodules are required to be connected by IPOS. As shown in Figure 7 for a k-submodule IPOS high-power PSFB converter. For an IPOS converter consisting of k PSFB converter submodules with the interleaved drive between the submodules, the phase difference of the drive pulses between every two submodules should be 2π/k. Since the frequency of the rectified output voltage of the PSFB converter is twice the switching frequency, the phase difference between adjacent modules in an IPOS converter composed of k PSFB converters should be π/k.

From the analysis in Section 2.1, Section 2.2 and Section 2.3, it is clear that for an IPOS converter consisting of two PSFB converter submodules, when the drive is interleaved between modules, the voltage of any rectifier diode in the module oscillates three times when the effective duty cycle of the secondary side $D_{eff}>0.5$. The first oscillation is mainly caused by the rectifier diode commutation of submodule M₁ itself; the second oscillation is mainly caused by the rectifier diode renewal of submodule M₂; and the third oscillation is mainly caused by the rectifier diode commutation of submodule M₂. It follows that for an IPOS system consisting of k sub-modules, when interleaved driving is used between the sub-modules, the voltage of any rectifier diode in the module oscillates k + 1 times at $D_{eff}>1/k$.

3. Suppression Technique of Rectifier Diode Spike Voltage

The effective suppression of rectifier diode spike voltage plays a crucial role in the design of high-power, medium-voltage, and high-voltage applications utilizing the PSFB converter. For the IPOS high-power PSFB converter under interleaved drive, the voltage of the rectifier diode oscillates three times when it operates at $D_{eff}>0.5$. If an active embedding strategy is used to suppress the rectifier diode spike voltage, the control circuit design will be very complicated. Considering the reliability of the system, the most efficient way to suppress the rectifier diode spike voltage in IPOS high-power PSFB converters is to connect an RCD buffer circuit in parallel behind the rectifier bridge.

3.1. Design of RCD Buffer Circuit

From Equations (7), (12), and (18), the three extreme values of the primary side current $i_{p1}$ of submodule M₁, $i_{p\mathrm{I}}$, $i_{p\mathrm{II}}$ and $i_{p\mathrm{III}}$, respectively, are:

$$i_{p\mathrm{I}}=n{i}_{Lf}(t-t_1)+n{V}_{in}\sqrt{\frac{C_{j23}}{n^2{L}_{r1}}}+\frac{V_o-n{V}_{in}}{n^2{L}_{r2}+L_f}(t-t_1)$$

(20)

$$i_{p\mathrm{II}}=n{i}_{Lf}(t-t_3)+\frac{n^2{L}_{r1}(2n{V}_{in}-V_o)}{\left[2n^2(L_{r1}+L_{r2})+L_f\right]}\sqrt{\frac{C_{j23}}{n^2{L}_{r1}}}$$

(21)

$$i_{p\mathrm{III}}=n{i}_{Lf}(t-t_6)+\frac{n^2{L}_{r1}(V_o-n{V}_{in})}{n^2{L}_{r1}+L_f}\sqrt{\frac{C_{j23}}{n^2{L}_{r1}}}$$

(22)

They are composed of two parts: one for the filter inductor current $n{i}_{Lf}\left(t-t_a\right)\left(a=1,2,4\right)$ converted to the secondary, and the other for the resonant inductor and junction capacitor resonant operation. Since $L_r<<L_f$, the resonant current of the resonant inductor at the first resonant operation with the rectifier diode junction capacitor is larger than the resonant current at the second and third resonant operations, which makes the resonant inductor resonate with the rectifier diode junction capacitor for the first time with the maximum resonant spike voltage, i.e., the first spike voltage of the rectifier diode is the largest.

The RCD buffer circuit connected in parallel behind the rectifier bridge can buffer the three oscillations of the rectifier diode voltage, which not only does not require additional control circuits but also has a good buffering effect and high reliability. The rectifier bridge is followed by a parallel RCD buffer circuit, which is shown in Figure 8.

Because the rectifier diode breakdown voltage depends on the maximum value of the diode transient voltage, the IPOS high-power PSFB converter has the largest spike voltage at the first oscillation. Therefore, the design of the RCD buffer circuit focuses on the suppression of the first spike voltage. The circuit structure utilizes the buffer capacitor $C_s$ to absorb and store the energy from the primary resonant inductor, thereby reducing the spike voltage during diode turn-off. Therefore, the value of $C_s$ in the RCD buffer circuit should be much larger than the value of the diode junction capacitance to achieve a better spike voltage suppression effect. The design of the buffer capacitor $C_s$ and the discharge resistor $R_s$ is crucial to achieving the best buffering effect. A sketch of the voltage waveform across the rectifier diode and $C_s$ is shown in Figure 9.

The black curve and the red dashed line in Figure 9 are the voltage waveforms across the rectifier diode and $C_s$, respectively. The primary current of submodule M₁ increases to a value equal to the converted value of the secondary current at moment $t_1$. The resonant inductor $L_{r1}$ resonates with the junction capacitors $C_{j2}$ and $C_{j3}$ of rectifier diodes D₂ and D₃, charging the junction capacitors $C_{j2}$ and $C_{j3}$, and the voltage across the diodes starts to rise. The moment when $C_s$ participates in resonance is $t_2$, and the moment when $C_s$ starts to discharge is $t_x$.

3.2. Working Process of RCD Buffer Circuit

With the RCD buffer circuit connected in parallel behind the rectifier bridge, $C_s$ has two completely same charge/discharge cycles in one switching cycle, and the energy absorbed and released in one charge/discharge cycle is the same. The choice of $C_s$ and $R_s$ is mainly related to the energy absorbed or discharged during one charge/discharge. Based on the relationship between the charged energy of $C_s$ and the discharged energy of $C_s,$ an algebraic equation is established to obtain the relationship between the spike voltage, $R_s$, and $C_s$. Using this equation, the design of buffer capacitors and discharge resistors within the RCD buffer circuit can be realized to achieve effective suppression and prediction of diode spike voltage values.

The oscillation process of the diode voltage after adding the RCD buffer circuit can be divided into 3 stages.

(1) Stage 1: The $C_{j23}$ voltage is smaller than the $C_s$ voltage; only $C_{j23}$ is involved in resonance, i.e., the [$t_1$–$t_2$] period in Figure 9.

(2) Stage 2: The $C_{j23}$ voltage is slightly greater than the $C_s$ voltage, diode D_s turns on, and then $C_{j23}$ and $C_s$ at the same time participate in resonance, that is, the [$t_2$–$t_x$] period in Figure 9.

(3) Stage 3: The energy of the resonant part of the resonant inductor L_r1 has all been transferred to the capacitor. The capacitors $C_{j23}$ and $C_s$ start to discharge at this stage, and the capacitor voltage starts to drop. Since the discharge circuit of $C_{j23}$ is different from that of $C_s$, and $C_{j23}<<C_s$, entering this stage, the voltage across $C_{j23}$ is less than the voltage across $C_s$, and the diode D_s turns off. The time starting point of this stage is the $t_2$ moment in Figure 9.

The rectifier diode spike voltage appears at the moment when all the energy involved in the resonant part of the inductor is transferred to the capacitor. The value of the inductor current is equal to the value at the moment of $t_1$, and the voltage at both ends of the capacitor involved in resonance begins to fall. Stage 2 is the charging process of buffer capacitor $C_s$, and the energy charged into $C_s$ as:

$$\Delta E_{Cs\_in}=\frac{1}{2}{C}_s{V}_{Cs}^2(t_x)-\frac{1}{2}{C}_s{V}_{Csmin}^2$$

(23)

The energy of the resonant inductor Lr’s resonant part has been fully transferred to the capacitor at the moment $t_x$. In this stage, the rectifier diode junction capacitors C_j23 and $C_s$ start to discharge, and the capacitor voltage starts to drop. Since the discharge circuits of $C_{j23}$ and $C_s$ are different, and $C_{j23}<<C_s$, after entering this stage, the voltage across $C_{j23}$ is less than the voltage across $C_s$, and the diode D_s turns off.

Since the time from $t_2$ to $t_x$ is much smaller than the switching period, the charging time of $C_s$ is ignored when analyzing the discharge process. Because none of the components on the primary side of the transformer participate in the discharge process of $C_s$, only the circuit state on the secondary side of the transformer is analyzed when discussing the discharge process. The time scale of $C_s$ discharge is much larger than the resonant period, and the effect of resonance is ignored when analyzing the discharge process. Based on the different states of the transformer, the discharge phase of $C_s$ can be analyzed in two processes.

Discharge process 1: The voltage on the secondary side of the transformer is not 0, and the voltage at the output of the rectifier bridge is $n{V}_{in}$; Because the capacitance of $C_s$ is large enough, the voltage change across C_s is small throughout the charging and discharging processes. $C_s$ in the discharge state is equivalent to a voltage source, whose value can be approximated as $V_{Cs}\left(t_x\right)=V_{Csmin}+\Delta V_{cs}$, where $\Delta V_{cs}$ is the amount of change in voltage across $C_s$. For an IPOS converter consisting of two PSFB converter submodules, the output voltage corresponding to a single submodule is approximated as $V_o/2$. The equivalent circuit for discharge process 1 is shown in Figure 10.

In discharge process 1, the energy discharged by $C_s$$E_1$ is:

$$E_1=\frac{V_o{V}_{Cs}(t_x)\cdot (V_{Cs}(t_x)-n{V}_{in})}{4n{V}_{in}{R}_s{f}_s}$$

(24)

Discharge process 2: The discharge process transformer’s secondary voltage is 0, and the energy released by $C_s$ is the energy consumed by $R_s$. The equivalent circuit of discharge process 2 is shown in Figure 11.

In discharge process 2, the energy discharged by $C_s$$E_2$ is:

$$E_2=\frac{V_{Cs}^2(t_x)}{2R_s{f}_s}\cdot (1-\frac{V_o}{2n{V}_{in}})$$

(25)

The energy discharged from the buffer capacitor $C_s$ during one discharge is:

$$\Delta E_{Cs\_out}=E_1+E_2=\frac{V_{Cs}(t_x)}{2R_s{f}_s}(V_{Cs}(t_x)-\frac{V_0}{2})$$

(26)

The energy absorbed and discharged by the buffer capacitor $C_s$ is equal in half a switching cycle, and the relationship between the variation of the spike voltage $V_{Cs}\left(t\right)$ with $C_s$ and $R_s$ is obtained by $\Delta E_{Cs\_in}=\Delta E_{Cs\_out}$. The surface plot of the variation of $V_{Cs}\left(t\right)$ with $R_s$ and $C_s$ is shown in Figure 12 by substituting the data in

Table 1. Key parameters of the 100 kW prototype.

Parameter	Value
$\mathrm{Input}\mathrm{voltage}{V}_{in}$	240 V
$\mathrm{Output}\mathrm{voltage}{V}_o$	2000 V
Transformer ratio 1:n	1:6
$\mathrm{Switching}\mathrm{frequency}{f}_s$	15 kHz
$\mathrm{Transformer}\mathrm{leakage}\mathrm{inductance}{L}_r$	2 μH
$\mathrm{Buffer}\mathrm{capacitance}{C}_s$	0.9 μF
$\mathrm{Discharge}\mathrm{resistance}{R}_s$	4.7 kΩ
$\mathrm{Rectifier}\mathrm{diode}\mathrm{junction}\mathrm{capacitance}{C}_j$	630 pF
$\mathrm{Rated}\mathrm{power}{P}_n$	100 kW

.

Under certain operating conditions, as can be seen from Figure 12. In the RCD buffer circuit, when the value of $C_s$ is certain, the smaller $R_s$, the more energy the buffer capacitor releases through the discharge resistor. The buffer capacitor can participate in the resonance earlier, and the buffer effect is better. But the smaller $R_s$, the more energy is consumed on it, and the lower the efficiency. When $R_s$ is certain, the smaller the $C_s$, the lower the voltage when the buffer capacitor is involved in the resonance. So, the $C_s$ can also participate in the resonance earlier, and the buffering effect of the RCD buffer circuit will be better. However, choosing too small a $C_s$ will not only lead to large voltage fluctuations in the buffer capacitor but also cause severe heating of the buffer capacitor and low system efficiency. Therefore, the design of the RCD buffer circuit should take into account the withstand voltage of the rectifier diode and choose a smaller buffer capacitor and resistor as much as the efficiency of the system allows. Thus, the suppression and prediction of diode spike voltage values can be achieved by $\Delta E_{Cs\_in}=\Delta E_{Cs\_out}$.

4. Experimental Verification

The correctness of the voltage oscillation mechanism of the rectifier diodes of the IPOS high-power PSFB converter and the accuracy of the prediction of the diode spike voltage values by $C_s$ and $R_s$ are verified on a 100 kW test prototype. Considering that commercially available fast recovery diodes typically have a maximum withstand voltage of 1700 V, two such diodes with a withstand voltage of 1700 V are connected in series for each rectifier diode in the test prototype. Table 1 presents the relevant parameters of the prototype.

Points to note during the test and the specifications of the measuring equipment are provided in [Appendix A.1 and Appendix A.2]. Figure 13 shows the picture of the 100 kW prototype topology and test stand; Figure 14 shows the waveforms of driving pulses of switch transistors S₁ and S₅; Figure 15 shows the waveforms of module output voltage, output current, and rectifier output voltage; and Figure 16 and Figure 17 show the waveforms of rectifier diode voltage and module rectifier output voltage.

Figure 14 provides the interleaved parallel drive waveforms of submodules M₁ and M₂ corresponding to switch transistors S₁ and S₅. The drive pulses of submodules M₁ and M₂ corresponding to switch transistors can be seen to be interleaved in phase by π/2. Figure 15 gives the module output voltage, module rectifier output voltage, and filter inductor current waveforms, and it can be seen that the inductor current ripple under the drive of interleaved pulses is four times the switching frequency when comparing Figure 14 and Figure 15. Figure 16 and Figure 17 show the voltage waveforms of rectifier diodes D₁, D₅, and D₆ and module rectifier output voltage $V_{rect}$. The change in amplitude of the diode voltage during the first and second oscillations is seen to increase and then decrease, while the change in amplitude during the third oscillation decreases and then increases. It is also clear from Figure 16 and Figure 17 that the voltage amplitude of the first oscillation of the diode voltage is greater than the voltage amplitude of the second and third oscillations. which is consistent with the conclusions analyzed in Section 2.

To verify the rationality of the buffer capacitor and discharge resistor configuration method in Section 3.2, based on the fact that the rectifier diode voltage does not exceed 2000 V, three combinations of $C_s$ and $R_s$ were selected from Figure 12. The predicted values of the corresponding rectifier diode spike voltages were given as shown in

Table 2. Prediction of rectifier diode spike voltage at different $C_s$ and $R_s$.

	Absorption Capacitance Cs (μF)	Discharge Resistance Rs (kΩ)	The Predicted Value of Spike Voltage (V)
a	0.9	4.7	1782
b	1.2	6.2	1841
c	1.4	7.5	1937

.

According to the three sets of $C_s$ and $R_s$ combinations selected in Table 2. Three sets of rectifier diode voltage spike prediction tests were done under the same operating conditions, and the test pictures are shown in Figure 18.

As shown in Figure 18a–c, the spike voltage across the rectifier diode D₁ increases as $C_s$ and $R_s$ increase, which is consistent with the conclusion drawn in Figure 12.

Table 3. Rectifier diode spike voltage test for different combinations of $C_s$ and $R_s$.

	Absorption Capacitance Cs (μF)	Discharge Resistance Rs (kΩ)	The Predicted Value of Spike Voltage (V)	Spike Voltage Error Rate (%)
a	0.9	4.7	1794	0.67
b	1.2	6.2	1857	0.87
c	1.4	7.5	1963	1.34

gives the tested values of the diode spike voltages and the voltage error rates of the predicted and tested values for different combinations of $R_s$ and $C_s$ corresponding to the subplots (a), (b) and (c) in Figure 18. The maximum error between the measured and predicted values of rectifier diode spike voltage can be seen to be only 1.34%, which is within the acceptable range in engineering applications.

5. Conclusions

This paper innovatively establishes the equivalent circuit model of the rectifier diode voltage parasitic oscillation of the IPOS high-power PSFB converter. It analyzes the mutual influence of rectifier diode voltage oscillations between submodules under interleaved control and investigates the mechanism behind multiple voltage oscillations. The following conclusions are drawn based on prototype testing:

(1)

By establishing the equivalent circuit of the parasitic oscillation of the rectifier diode of the IPOS high-power PSFB converter, it improves the precision of the analytical model of the parasitic oscillation of the rectifier diode voltage of the PSFB converter and provides an analytical idea of the parasitic oscillation of the rectifier diode voltage in the complex case of PSFB converters.

(2)

Revealing the mechanism of interplay and multiple oscillations of rectifier diode voltage in an IPOS high-power PSFB converter under interleaved control, and it agrees well with the experimental results.

(3)

The design method of $C_s$ and $R_s$ is obtained by analyzing the relationship between the rectifier diode spike voltage with $C_s$ and $R_s$. This method effectively predicts the spike voltage and avoids issues of insufficient margin or over margin in RCD buffer circuit design.

This paper investigates the mechanism of multiple oscillations of rectifier diode voltage and diode voltage spike suppression in an IPOS high-power PSFB converter under interleaved control and achieves certain results, but there are also some shortcomings and room for progress. The RCD buffer circuit reduces the efficiency of the system, so the next step is to find a better voltage spike suppression strategy.